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Commit Graph

96265 Commits

Author SHA1 Message Date
Matt Arsenault
e06d79aa83 Don't merge tiny functions.
It's silly to merge functions like these:

define void @foo(i32 %x) {
  ret void
}

define void @bar(i32 %x) {
  ret void
}

to get

define void @bar(i32) {
  tail call void @foo(i32 %0)
  ret void
}

llvm-svn: 191786
2013-10-01 18:05:30 +00:00
Rafael Espindola
1622afa564 Reverts commit r190808 and r190556.
The use of these features in clang has been reverted.

llvm-svn: 191785
2013-10-01 17:40:47 +00:00
Preston Gurd
c52dfda610 Add test case for PR16785.
Thanks for Dimitry Andric, Rafael Espindola, and Benjamin Kramer
for providing and progressively reducing the test case!

llvm-svn: 191782
2013-10-01 17:02:48 +00:00
Alexey Samsonov
ada9b94050 [DebugInfo] Simplify and speedup .debug_aranges parsing
Parsing .debug_aranges section now takes O(nlogn) operations instead
of O(n^2), where "n" is the number of address ranges. With this change,
the time required to symbolize an address from a random large
Clang-generated binary drops from 165 seconds to 1.5 seconds.

No functionality change.

llvm-svn: 191781
2013-10-01 16:52:46 +00:00
Andrew Kaylor
405da08c77 Fixing MCJIT multiple module linking for OSX
llvm-svn: 191780
2013-10-01 16:42:50 +00:00
Alexey Samsonov
1bb7484e09 [DebugInfo] Further simplify DWARFDebugAranges. No functionality change.
llvm-svn: 191779
2013-10-01 16:25:14 +00:00
Alexey Samsonov
18c4e7e84f [DebugInfo] Remove unused functions from DWARFDebugAranges and fix code style.
llvm-svn: 191778
2013-10-01 15:48:10 +00:00
Richard Sandiford
8ac2bcbe80 [SystemZ] Add comparisons of high words and memory
llvm-svn: 191777
2013-10-01 15:00:44 +00:00
Richard Sandiford
2ed79fb1d7 [SystemZ] Add comparisons of large immediates using high words
There are no corresponding patterns for small immediates because they would
prevent the use of fused compare-and-branch instructions.

llvm-svn: 191775
2013-10-01 14:56:23 +00:00
Richard Sandiford
3b7b53e6f4 [SystemZ] Add immediate addition involving high words
llvm-svn: 191774
2013-10-01 14:53:46 +00:00
Richard Sandiford
884566de6e [SystemZ] Extend test-under-mask support to high GR32s
llvm-svn: 191773
2013-10-01 14:41:52 +00:00
Richard Sandiford
d2e34690a4 [SystemZ] Extend 32-bit RISBG optimizations to high words
This involves using RISB[LH]G, whereas the equivalent z10 optimization
uses RISBG.

llvm-svn: 191770
2013-10-01 14:36:20 +00:00
Richard Sandiford
e2f5332463 [SystemZ] Extend pseudo conditional 8- and 16-bit stores to high words
As the comment says, we always want to use STOC for 32-bit stores.

llvm-svn: 191767
2013-10-01 14:33:55 +00:00
Tim Northover
684a0e633d ARM: support interrupt attribute
This function-attribute modifies the callee-saved register list and function
epilogue (specifically the return instruction) so that a routine is suitable
for use as an interrupt-handler of the specified type without disrupting
user-mode applications.

rdar://problem/14207019

llvm-svn: 191766
2013-10-01 14:33:28 +00:00
Richard Sandiford
5df2380d20 [SystemZ] Add test missing from r191764.
llvm-svn: 191765
2013-10-01 14:31:50 +00:00
Richard Sandiford
24e987020f [SystemZ] Optimize 32-bit FPR<->GPR moves for z196 and above
Floats are stored in the high 32 bits of an FPR, and the only GPR<->FPR
transfers are full-register transfers.  This patch optimizes GPR<->FPR
float transfers when the high word of a GPR is directly accessible.

llvm-svn: 191764
2013-10-01 14:31:11 +00:00
Tareq A. Siraj
2c204767da Add non-blocking Wait() for launched processes
- New ProcessInfo class to encapsulate information about child processes.
- Generalized the Wait() to support non-blocking wait on child processes.
- ExecuteNoWait() now returns a ProcessInfo object with information about
  the launched child. Users will be able to use this object to
  perform non-blocking wait.
- ExecuteNoWait() now accepts an ExecutionFailed param that tells if execution
  failed or not.

These changes will allow users to implement basic process parallel
tools.

Differential Revision: http://llvm-reviews.chandlerc.com/D1728

llvm-svn: 191763
2013-10-01 14:28:18 +00:00
Richard Sandiford
7125240faa [SystemZ] Allow integer AND involving high words
llvm-svn: 191762
2013-10-01 14:20:41 +00:00
Richard Sandiford
9d3cacb101 [SystemZ] Allow integer XOR involving high words
llvm-svn: 191759
2013-10-01 14:08:44 +00:00
Rafael Espindola
a279462828 Remove several unused variables.
Patch by Alp Toker.

llvm-svn: 191757
2013-10-01 13:32:03 +00:00
Richard Sandiford
d2a449d3de [SystemZ] Allow integer OR involving high words
llvm-svn: 191755
2013-10-01 13:22:41 +00:00
Richard Sandiford
3af32e8cab [SystemZ] Allow integer insertions with a high-word destination
llvm-svn: 191753
2013-10-01 13:18:56 +00:00
Sylvestre Ledru
804e76cb31 Fix a typo in the documentation. Thanks to Diana Vasile for the patch
llvm-svn: 191752
2013-10-01 13:17:09 +00:00
Richard Sandiford
497097c027 [SystemZ] Allow selects with a high-word destination
llvm-svn: 191751
2013-10-01 13:10:16 +00:00
Richard Sandiford
8c8e2f0237 [SystemZ] Add patterns to load a constant into a high word (IIHF)
Similar to low words, we can use the shorter LLIHL and LLIHH if it turns
out that the other half of the GR64 isn't live.

llvm-svn: 191750
2013-10-01 13:02:28 +00:00
Joey Gouly
7f15046246 [ARM] Remove an unused function from the disassembler.
Pointed out by Joerg.

llvm-svn: 191749
2013-10-01 13:01:10 +00:00
Matheus Almeida
7a5f5ed788 Test commit. Updated comment.
llvm-svn: 191748
2013-10-01 12:53:00 +00:00
Richard Sandiford
ac3360b004 [SystemZ] Add register zero extensions involving at least one high word
llvm-svn: 191746
2013-10-01 12:49:07 +00:00
Joey Gouly
12afb60cf2 [ARM] Introduce the 'sevl' instruction in ARMv8.
This also removes the restriction on the immediate field of the 'hint'
instruction.

llvm-svn: 191744
2013-10-01 12:39:11 +00:00
Richard Sandiford
192be1070b [SystemZ] Add truncating high-word stores (STCH and STHH)
llvm-svn: 191743
2013-10-01 12:22:49 +00:00
Richard Sandiford
de433bf58d [SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
llvm-svn: 191742
2013-10-01 12:19:08 +00:00
Benjamin Kramer
e04c4c3faf SCEVExpander: Fix a regression I introduced by to eagerly adding RAII objects.
PR17425.

llvm-svn: 191741
2013-10-01 12:17:11 +00:00
Richard Sandiford
dd8ae7a617 [SystemZ] Add sign-extending high-word loads (LBH and LHH)
llvm-svn: 191740
2013-10-01 12:11:47 +00:00
Richard Sandiford
c2e496f7ba [SystemZ] Use upper words of GR64s for codegen
This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store).  The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.

The easiest way of testing this seemed to be add a new "h" register
constraint for high words.  I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.

llvm-svn: 191739
2013-10-01 11:26:28 +00:00
Richard Sandiford
21933530e5 [SystemZ] Reapply: Add definitions of LFH and STFH
Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts.  That should have been fixed by r191735.

llvm-svn: 191738
2013-10-01 10:31:04 +00:00
Daniel Sanders
6ffe6fc99c [mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
llvm-svn: 191737
2013-10-01 10:22:35 +00:00
Richard Sandiford
ffc286beba Fix pattern sort in DAGISelEmitter.cpp
The old code skipped one of the sorting criteria if either pattern had
no types.  This could lead to cycles of the form X < Y, Y < Z, Z < X.

llvm-svn: 191735
2013-10-01 09:49:01 +00:00
Vladimir Medic
fe4fd5260f This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
llvm-svn: 191734
2013-10-01 09:48:56 +00:00
Elena Demikhovsky
84c6cd222d AVX-512: Added X86vzmovl patterns
llvm-svn: 191733
2013-10-01 08:38:02 +00:00
Craig Topper
e1e883da01 Remove 0 as a valid encoding for the m-mmmm field.
llvm-svn: 191732
2013-10-01 07:10:28 +00:00
Craig Topper
419f67b3cc Remove unneeded fields from disassembler internal instruction format.
llvm-svn: 191731
2013-10-01 06:56:57 +00:00
Craig Topper
401688a9b1 BEXTR should be defined to take same type for bother operands.
llvm-svn: 191728
2013-10-01 03:48:26 +00:00
Tom Stellard
1e84b314be SelectionDAG: Clarify comments from r191600
llvm-svn: 191724
2013-10-01 02:09:00 +00:00
Andrew Kaylor
6f0e782b64 Tests for MCJIT multiple module support
llvm-svn: 191723
2013-10-01 01:48:36 +00:00
Andrew Kaylor
b068069d0c Adding multiple module support for MCJIT.
Tests to follow.

PIC with small code model and  EH frame handling will not work with multiple modules.  There are also some rough edges to be smoothed out for remote target support.

llvm-svn: 191722
2013-10-01 01:47:35 +00:00
Eric Christopher
f7c4656096 Add the DW_AT_GNU_ranges_base attribute if we've emitted any ranges
into the debug_ranges section.

llvm-svn: 191721
2013-10-01 00:43:36 +00:00
Eric Christopher
ff4531d2fa Update comments.
llvm-svn: 191720
2013-10-01 00:43:31 +00:00
Matt Arsenault
a3e171a6c8 Fix code duplication
llvm-svn: 191716
2013-10-01 00:01:14 +00:00
Preston Gurd
182f111d29 Forgot to add a break statement.
llvm-svn: 191715
2013-09-30 23:51:22 +00:00
Matt Arsenault
19f03c0f9c Use CHECK-LABEL
llvm-svn: 191713
2013-09-30 23:31:55 +00:00