Vincent Lejeune
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3ca0b82e8b
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R600: Use SchedModel enum for is{Trans,Vector}Only functions
llvm-svn: 189979
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2013-09-04 19:53:30 +00:00 |
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Tom Stellard
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38c07cc5d7
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R600: Add support for i8 and i16 local memory stores
llvm-svn: 189223
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2013-08-26 15:05:49 +00:00 |
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Tom Stellard
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291737ed45
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R600: Add IsExport bit to TableGen instruction definitions
Tested-by: Aaron Watry <awatry@gmail.com>
llvm-svn: 188516
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2013-08-16 01:11:51 +00:00 |
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Tom Stellard
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16a304af0c
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Revert "R600: Use SchedModel enum for is{Trans,Vector}Only functions"
This reverts commit 3f1de26cb5cc0543a6a1d71259a7a39d97139051.
llvm-svn: 187524
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2013-07-31 20:43:03 +00:00 |
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Vincent Lejeune
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5879083446
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R600: Use SchedModel enum for is{Trans,Vector}Only functions
llvm-svn: 187512
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2013-07-31 19:31:35 +00:00 |
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Tom Stellard
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99f122e9be
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R600: Add local memory support via LDS
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185162
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2013-06-28 15:47:08 +00:00 |
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Tom Stellard
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204ca3185b
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R600: Add ALUInst bit to tablegen definitions v2
v2:
- Remove functions left over from a previous rebase.
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 185160
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2013-06-28 15:46:53 +00:00 |
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Tom Stellard
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428a19228a
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R600: Use correct encoding for Vertex Fetch instructions on Cayman
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184016
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2013-06-14 22:12:30 +00:00 |
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Tom Stellard
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a3b0b87105
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R600: Factor the instruction encoding out the RAT_WRITE_CACHELESS_eg class
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184014
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2013-06-14 22:12:19 +00:00 |
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Tom Stellard
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9f063c72c3
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R600: Move instruction encoding definitions into a separate .td file
Reviewed-by: Vincent Lejeune<vljn at ovi.com>
llvm-svn: 184013
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2013-06-14 22:12:09 +00:00 |
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