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124 Commits

Author SHA1 Message Date
Chris Lattner
14310afe42 rename isLoad -> isSimpleLoad due to evan's desire to have such a predicate. 
llvm-svn: 45667
 2008-01-06 23:38:27 +00:00
Chris Lattner
5489888580 rename isStore -> mayStore to more accurately reflect what it captures. 
llvm-svn: 45656
 2008-01-06 08:36:04 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Bill Wendling
ec8be72a8b As per feedback, revised comments to (hopefully) make the different side effect 
flags clearer.

llvm-svn: 45120
 2007-12-17 21:02:07 +00:00
Bill Wendling
c8c611e88f Add flags to indicate that there are "never" side effects or that there "may be" 
side effects for machine instructions.

llvm-svn: 45022
 2007-12-14 01:48:59 +00:00
Evan Cheng
64a1febf9a Implicit def instructions, e.g. X86::IMPLICIT_DEF_GR32, are always re-materializable and they should not be spilled. 
llvm-svn: 44960
 2007-12-12 23:12:09 +00:00
Owen Anderson
aba398a5ce Add a flag for indirect branch instructions. 
Target maintainers: please check that the instructions for your target are correctly marked.

llvm-svn: 44012
 2007-11-12 07:39:39 +00:00
Anton Korobeynikov
a4eb4336d2 Clarify the meaning of '-2' register number 
llvm-svn: 43998
 2007-11-11 19:53:50 +00:00
Anton Korobeynikov
8e8473c783 Use TableGen to emit information for dwarf register numbers. 
This makes DwarfRegNum to accept list of numbers instead.
Added three different "flavours", but only slightly tested on x86-32/linux.
Please check another subtargets if possible,

llvm-svn: 43997
 2007-11-11 19:50:10 +00:00
Evan Cheng
859720c33b Add CopyCost to TargetRegisterClass. This specifies the cost of copying a value 
between two registers in the specific class.

llvm-svn: 42123
 2007-09-19 01:35:01 +00:00
Evan Cheng
b43255bc68 Remove (somewhat confusing) Imp<> helper, use let Defs = [], Uses = [] instead. 
llvm-svn: 41863
 2007-09-11 19:55:27 +00:00
Christopher Lamb
9a0d88efde Add target independent MachineInstr's to represent subreg insert/extract in MBB's. PR1350 
llvm-svn: 40518
 2007-07-26 07:48:21 +00:00
Evan Cheng
53cb03b583 No more noResults. 
llvm-svn: 40132
 2007-07-21 00:34:19 +00:00
Evan Cheng
8312ed6f77 Change instruction description to split OperandList into OutOperandList and 
InOperandList. This gives one piece of important information: # of results
produced by an instruction.
An example of the change:
def ADD32rr  : I<0x01, MRMDestReg, (ops GR32:$dst, GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;
=>
def ADD32rr  : I<0x01, MRMDestReg, (outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
                 "add{l} {$src2, $dst|$dst, $src2}",
                 [(set GR32:$dst, (add GR32:$src1, GR32:$src2))]>;

llvm-svn: 40033
 2007-07-19 01:14:50 +00:00
Evan Cheng
0ab209fa54 Remove clobbersPred. 
llvm-svn: 38500
 2007-07-10 18:07:08 +00:00
Evan Cheng
776d4d6e11 Do away with ImmutablePredicateOperand. 
llvm-svn: 37959
 2007-07-06 23:21:02 +00:00
Evan Cheng
0adaea7381 Add OptionalDefOperand to stand for optionally defined result. 
llvm-svn: 37930
 2007-07-06 01:00:16 +00:00
Evan Cheng
8b0cbaff08 - Added zero_reg def to stand for register 0. 
- Added two variants of PredicateOperand: ImmutablePredicateOperand, whose predicate does not change after isel; PredicateDefOperand, which represent a predicate defintion operand.

llvm-svn: 37892
 2007-07-05 07:09:09 +00:00
Dan Gohman
9cbc3fb1ab Revert the earlier change that removed the M_REMATERIALIZABLE machine 
instruction flag, and use the flag along with a virtual member function
hook for targets to override if there are instructions that are only
trivially rematerializable with specific operands (i.e. constant pool
loads).

llvm-svn: 37728
 2007-06-26 00:48:07 +00:00
Dan Gohman
b60d8a92c9 Replace M_REMATERIALIZIBLE and the newly-added isOtherReMaterializableLoad 
with a general target hook to identify rematerializable instructions. Some
instructions are only rematerializable with specific operands, such as loads
from constant pools, while others are always rematerializable. This hook
allows both to be identified as being rematerializable with the same
mechanism.

llvm-svn: 37644
 2007-06-19 01:48:05 +00:00
Evan Cheng
12b3002673 Replace TargetInstrInfo::CanBeDuplicated() with a M_NOT_DUPLICABLE bit. 
llvm-svn: 37643
 2007-06-19 01:26:51 +00:00
Christopher Lamb
68017d151b Add support to tablegen for specifying subregister classes on a per register class basis. 
llvm-svn: 37572
 2007-06-13 22:20:15 +00:00
Evan Cheng
055d2fc508 Added clobbersPred. 
llvm-svn: 37466
 2007-06-06 10:15:28 +00:00
Evan Cheng
0aced52f41 Added isPredicable bit to class Instruction. 
llvm-svn: 37117
 2007-05-16 20:47:01 +00:00
Evan Cheng
4dd52e052f PredicateOperand can be used as a normal operand for isel. 
llvm-svn: 36947
 2007-05-08 21:06:08 +00:00
Bill Wendling
dc82c5a195 Add an "implies" field to features. This indicates that, if the current 
feature is set, then the features in the implied list should be set also.
The opposite is also enforced: if a feature in the implied list isn't set,
then the feature that owns that implies list shouldn't be set either.

llvm-svn: 36756
 2007-05-04 20:38:40 +00:00
Chris Lattner
0b2b0185a0 expose HonorSignDependentRoundingFPMathOption to .td files 
llvm-svn: 36658
 2007-05-03 00:27:11 +00:00
Nate Begeman
767ee95d29 llvm bug #1350, parts 1, 2, and 3. 
llvm-svn: 36618
 2007-05-01 05:57:02 +00:00
Evan Cheng
842e2c48a0 Add sub-registers sets. 
llvm-svn: 36278
 2007-04-20 21:13:46 +00:00
Evan Cheng
498f19548c Added isReMaterializable. 
llvm-svn: 35160
 2007-03-19 06:22:07 +00:00
Chris Lattner
90c768b913 Add calling convention info 
llvm-svn: 34661
 2007-02-27 06:59:52 +00:00
Dan Gohman
e24135a647 Fix typos in comments. 
llvm-svn: 34456
 2007-02-20 20:52:03 +00:00
Jim Laskey
23ed7d2625 Make LABEL a builtin opcode. 
llvm-svn: 33537
 2007-01-26 14:34:52 +00:00
Evan Cheng
0241c4a0b5 Comment. 
llvm-svn: 33114
 2007-01-12 07:25:16 +00:00
Chris Lattner
1158705ea7 add a new field needed by the code emitter generator. 
llvm-svn: 31768
 2006-11-15 22:55:04 +00:00
Chris Lattner
4296d2e0fa initial steps to getting the predicate on PPC::BLR right. 
llvm-svn: 31437
 2006-11-03 23:52:18 +00:00
Chris Lattner
f9394871ff remove dead var 
llvm-svn: 31436
 2006-11-03 23:50:15 +00:00
Evan Cheng
f49cb35d90 Add constraints to Instruction class. 
llvm-svn: 31332
 2006-11-01 00:26:27 +00:00
Chris Lattner
b25677f5ca Move the Imp tblgen class from the X86 backend to common code. 
llvm-svn: 30907
 2006-10-12 17:49:27 +00:00
Evan Cheng
abd650f034 Add code size to target instruction use it as the 3rd isel sorting tie-breaker. 
llvm-svn: 29193
 2006-07-19 00:24:41 +00:00
Evan Cheng
4bbd1c455f Added a Flags field to TargetOperandInfo. Currently the only flag is 
M_LOOK_UP_PTR_REG_CLASS which allows the register class of the operand to be
resolved via a callback at runtime.

llvm-svn: 28387
 2006-05-18 20:44:26 +00:00
Evan Cheng
89187d589f Remove CalleeSavedRegisters from class Target. 
llvm-svn: 28377
 2006-05-18 00:09:53 +00:00
Evan Cheng
ea24815aa3 Remove PointerType from class Target 
llvm-svn: 28368
 2006-05-17 21:20:27 +00:00
Vladimir Prus
15fdb12773 Replace "../whatever.td" with "whatever.td", so that out-of-tree backends 
can just add lib/Target to TableGen includes.

llvm-svn: 28318
 2006-05-16 06:39:36 +00:00
Chris Lattner
676c3dfd68 Improve comment, patch provided by Vladimir Prus! 
llvm-svn: 28307
 2006-05-15 18:35:02 +00:00
Chris Lattner
3fe38bf77b Update comment. 
llvm-svn: 28283
 2006-05-14 02:05:19 +00:00
Chris Lattner
8456272509 Put PHI/INLINEASM into the correct namespace. 
llvm-svn: 28037
 2006-05-01 17:00:49 +00:00
Evan Cheng
5e80563052 Renamed AddedCost to AddedComplexity. 
llvm-svn: 27843
 2006-04-19 20:38:28 +00:00
Evan Cheng
318120f8ad Allow "let AddedCost = n in" to increase pattern complexity. 
llvm-svn: 27834
 2006-04-19 18:07:24 +00:00
Jim Laskey
d577317f38 Add support for dwarf register numbering. 
llvm-svn: 27080
 2006-03-24 21:13:21 +00:00