Tom Stellard
9943755afb
AMDGPU/SI: Detect uniform branches and emit s_cbranch instructions
...
Reviewers: arsenm
Subscribers: mareko, MatzeB, qcolombet, arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D16603
llvm-svn: 260765
2016-02-12 23:45:29 +00:00
Matt Arsenault
51a14cbbc7
AMDGPU: Make v32i8/v64i8 illegal types
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Old intrinsics were forcing these, but they have now all
been removed. This fixes large i8 vector operations generally
being broken.
llvm-svn: 258788
2016-01-26 04:43:48 +00:00
Tom Stellard
e81c016153
AMDGPU/SI: Fix encoding for FLAT_SCRATCH registers on VI
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Summary:
These register has different encodings on CI and VI, so we add pseudo
FLAT_SCRACTH registers to be used before MC, and subtarget specific
registers to be used by the MC layer.
Reviewers: arsenm
Subscribers: arsenm, llvm-commits
Differential Revision: http://reviews.llvm.org/D15661
llvm-svn: 256178
2015-12-21 18:44:27 +00:00
Tom Stellard
e5c23ab1eb
AMDGPU/SI: Change assembly name for flat scratch registers to flat_scratch
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This matches what the assembler accepts.
llvm-svn: 256177
2015-12-21 18:44:21 +00:00
Matt Arsenault
538dc413bb
AMDGPU: Make v2i64/v2f64 legal types.
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They can be loaded and stored, so count them as legal. This is
mostly to fix a number of common cases for load/store merging.
llvm-svn: 254086
2015-11-25 19:58:34 +00:00
Tom Stellard
375168229e
Revert "Remove unnecessary call to getAllocatableRegClass"
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This reverts commit r252565.
This also includes the revert of the commit mentioned below in order to
avoid breaking tests in AMDGPU:
Revert "AMDGPU: Set isAllocatable = 0 on VS_32/VS_64"
This reverts commit r252674.
llvm-svn: 252956
2015-11-12 21:43:25 +00:00
Matt Arsenault
01b2f20bdc
AMDGPU: Set isAllocatable = 0 on VS_32/VS_64
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llvm-svn: 252674
2015-11-11 00:01:32 +00:00
Matt Arsenault
a7afaaa71a
AMDGPU: Fix hardcoded alignment of spill.
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Instead of forcing 4 alignment when spilled, set register class
alignments.
llvm-svn: 252322
2015-11-06 17:54:47 +00:00
Matt Arsenault
e66b0aba3a
AMDGPU: Define correct number of SGPRs
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There are actually 104 so 2 were missing.
More assembler tests with high register number tuples
will be included in later patches.
llvm-svn: 251999
2015-11-03 22:39:50 +00:00
Matt Arsenault
8248804482
AMDGPU: Set CopyCost of register classes
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These require multiple mov instructions to copy,
but the default value is that 1 instruction is needed.
I'm not sure if this actually changes anything.
llvm-svn: 248651
2015-09-26 04:09:34 +00:00
Matt Arsenault
c1696e995e
AMDGPU/SI: Fix input vcc operand for VOP2b instructions
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Adds vcc to output string input for e32. Allows option
of using e64 encoding with assembler.
Also fixes these instructions not implicitly reading exec.
llvm-svn: 247074
2015-09-08 21:15:00 +00:00
Matt Arsenault
b0ba266970
AMDGPU/SI: Remove VCCReg
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llvm-svn: 244380
2015-08-08 00:41:48 +00:00
Matt Arsenault
ec3023a130
AMDGPU/SI: Remove source uses of VCCReg
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llvm-svn: 244379
2015-08-08 00:41:45 +00:00
Matt Arsenault
5da7c5df39
AMDGPU/SI: Remove EXECReg
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For the same reasons as the other physical registers.
llvm-svn: 244062
2015-08-05 16:42:57 +00:00
Matt Arsenault
1bf5500e99
AMDGPU: Remove SCCReg.
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These should be handled as a physical register rather
than a virtual register class with one member.
llvm-svn: 244061
2015-08-05 16:42:54 +00:00
Matt Arsenault
a0793d32be
AMDGPU/SI: Set DwarfRegNum
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This requires a fix in tablegen for the cast<int> from bits<16>
to work in the list initializer.
llvm-svn: 243723
2015-07-31 01:12:10 +00:00
Tom Stellard
3f1708598e
R600 -> AMDGPU rename
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llvm-svn: 239657
2015-06-13 03:28:10 +00:00
Tom Stellard
39f7e52397
Revert "AMDGPU: Add core backend files for R600/SI codegen v6"
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This reverts commit 4ea70107c5e51230e9e60f0bf58a0f74aa4885ea.
llvm-svn: 160303
2012-07-16 18:19:53 +00:00
Tom Stellard
9f326179fc
AMDGPU: Add core backend files for R600/SI codegen v6
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llvm-svn: 160270
2012-07-16 14:17:08 +00:00