Chris Lattner
9cf60e3459
Fix some bugs andrew noticed legalizing memset for alpha
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llvm-svn: 19969
2005-02-01 18:38:28 +00:00
Chris Lattner
382abe80a0
Improve conformance with the Misha spelling benchmark suite
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llvm-svn: 19930
2005-01-30 00:09:23 +00:00
Chris Lattner
8200976176
adjust to ilist changes.
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llvm-svn: 19924
2005-01-29 18:41:25 +00:00
Chris Lattner
2755fb4171
Alpha doesn't have a native f32 extload instruction.
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llvm-svn: 19880
2005-01-28 22:58:25 +00:00
Chris Lattner
da7b5277c1
implement legalization of truncates whose results and sources need to be
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truncated, e.g. (truncate:i8 something:i16) on a 32 or 64-bit RISC.
llvm-svn: 19879
2005-01-28 22:52:50 +00:00
Chris Lattner
89cac82479
Get alpha working with memset/memcpy/memmove
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llvm-svn: 19878
2005-01-28 22:29:18 +00:00
Chris Lattner
4134789c8f
CopyFromReg produces two values. Make sure that we remember that both are
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legalized, and actually return the correct result when we legalize the chain first.
llvm-svn: 19866
2005-01-28 06:27:38 +00:00
Chris Lattner
849899e193
Silence optimized warnings.
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llvm-svn: 19797
2005-01-23 23:19:44 +00:00
Chris Lattner
65fc8007cd
Simplify/speedup the PEI by not having to scan for uses of the callee saved
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registers. This information is computed directly by the register allocator
now.
llvm-svn: 19795
2005-01-23 23:13:12 +00:00
Chris Lattner
556679b89d
Update physregsused info.
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llvm-svn: 19793
2005-01-23 22:55:45 +00:00
Chris Lattner
cc22be2981
Update this pass to set PhysRegsUsed info in MachineFunction.
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llvm-svn: 19792
2005-01-23 22:51:56 +00:00
Chris Lattner
964297fc32
Update these register allocators to set the PhysRegUsed info in MachineFunction.
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llvm-svn: 19791
2005-01-23 22:45:13 +00:00
Chris Lattner
6a6d5cf9eb
Add support for the PhysRegsUsed array.
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llvm-svn: 19789
2005-01-23 22:13:58 +00:00
Chris Lattner
c187b917f2
Speed this up a bit by making ModifiedRegs a vector<char> not vector<bool>
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llvm-svn: 19787
2005-01-23 21:45:01 +00:00
Chris Lattner
b3a5fc3ec0
Adjust to changes in SelectionDAG interfaces
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The first half of correct chain insertion for libcalls. This is not enough
to fix Fhourstones yet though.
llvm-svn: 19781
2005-01-23 04:42:50 +00:00
Chris Lattner
3165569ba9
Remove the 3 HACK HACK HACKs I put in before, fixing them properly with
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the new TLI that is available.
Implement support for handling out of range shifts. This allows us to
compile this code (a 64-bit rotate):
unsigned long long f3(unsigned long long x) {
return (x << 32) | (x >> (64-32));
}
into this:
f3:
mov %EDX, DWORD PTR [%ESP + 4]
mov %EAX, DWORD PTR [%ESP + 8]
ret
GCC produces this:
$ gcc t.c -masm=intel -O3 -S -o - -fomit-frame-pointer
..
f3:
push %ebx
mov %ebx, DWORD PTR [%esp+12]
mov %ecx, DWORD PTR [%esp+8]
mov %eax, %ebx
mov %edx, %ecx
pop %ebx
ret
The Simple ISEL produces (eww gross):
f3:
sub %ESP, 4
mov DWORD PTR [%ESP], %ESI
mov %EDX, DWORD PTR [%ESP + 8]
mov %ECX, DWORD PTR [%ESP + 12]
mov %EAX, 0
mov %ESI, 0
or %EAX, %ECX
or %EDX, %ESI
mov %ESI, DWORD PTR [%ESP]
add %ESP, 4
ret
llvm-svn: 19780
2005-01-23 04:39:44 +00:00
Chris Lattner
4c997d281c
Adjust to changes in SelectionDAG interface.
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llvm-svn: 19779
2005-01-23 04:36:26 +00:00
Chris Lattner
63ec3c402b
Get this to work for 64-bit systems.
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llvm-svn: 19763
2005-01-22 23:04:37 +00:00
Chris Lattner
29d6389d78
Implicitly defined registers can clobber callee saved registers too!
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This fixes the return-address-not-being-saved problem in the Alpha backend.
llvm-svn: 19741
2005-01-22 00:49:16 +00:00
Chris Lattner
97f35a7a07
More bugfixes for IA64 shifts.
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llvm-svn: 19739
2005-01-22 00:33:03 +00:00
Chris Lattner
67deea9d05
Fix problems with non-x86 targets.
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llvm-svn: 19738
2005-01-22 00:31:52 +00:00
Chris Lattner
42e239ed58
Add a nasty hack to fix Alpha/IA64 multiplies by a power of two.
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llvm-svn: 19737
2005-01-22 00:20:42 +00:00
Chris Lattner
e724100870
Remove unneeded line.
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llvm-svn: 19736
2005-01-21 23:43:12 +00:00
Chris Lattner
a974e215a5
test commit
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llvm-svn: 19735
2005-01-21 23:38:56 +00:00
Chris Lattner
392ddf430b
Unary token factor nodes are unneeded.
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llvm-svn: 19727
2005-01-21 18:01:22 +00:00
Chris Lattner
07c35617d5
Refactor libcall code a bit. Initial implementation of expanding int -> FP
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operations for 64-bit integers.
llvm-svn: 19724
2005-01-21 06:05:23 +00:00
Chris Lattner
6258ec2e1d
Simplify the shift-expansion code.
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llvm-svn: 19721
2005-01-20 20:29:23 +00:00
Chris Lattner
c95c7c90c9
Expand add/sub into ADD_PARTS/SUB_PARTS instead of a non-existant libcall.
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llvm-svn: 19715
2005-01-20 18:52:28 +00:00
Chris Lattner
4086a7a803
implement add_parts/sub_parts.
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llvm-svn: 19714
2005-01-20 18:50:55 +00:00
Chris Lattner
e7ce5d0e4c
Add missing entry.
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llvm-svn: 19712
2005-01-20 17:32:28 +00:00
Chris Lattner
e5212a16a2
Support targets that do not use i8 shift amounts.
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llvm-svn: 19707
2005-01-19 22:31:21 +00:00
Chris Lattner
0e7435bc5b
Add an assertion that would have made more sense to duraid
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llvm-svn: 19704
2005-01-19 21:32:07 +00:00
Chris Lattner
c662697319
Add support for targets that pass args in registers to calls.
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llvm-svn: 19703
2005-01-19 20:24:35 +00:00
Chris Lattner
277ac2be70
Fold single use token factor nodes into other token factor nodes.
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llvm-svn: 19701
2005-01-19 19:10:54 +00:00
Chris Lattner
85e0771f79
Realize the individual pieces of an expanded copytoreg/store/load are
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independent of each other.
llvm-svn: 19700
2005-01-19 18:02:17 +00:00
Chris Lattner
027c97e93e
Know some identities about tokenfactor nodes.
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llvm-svn: 19699
2005-01-19 18:01:40 +00:00
Chris Lattner
7114e8a527
Know some simple identities. This improves codegen for (1LL << N).
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llvm-svn: 19698
2005-01-19 17:29:49 +00:00
Chris Lattner
e97ed92617
Just in case, handle something that is both a use and a def.
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llvm-svn: 19696
2005-01-19 17:11:51 +00:00
Chris Lattner
2cb11bd2b9
When an instruction moves, make sure to update the VarInfo::Kills list as
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well as all of teh other stuff in livevar. This fixes the compiler crash
on fourinarow last night.
llvm-svn: 19695
2005-01-19 17:09:15 +00:00
Chris Lattner
408325ffdf
Use the TargetInstrInfo::commuteInstruction method to commute instructions
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instead of doing it manually.
llvm-svn: 19685
2005-01-19 07:08:42 +00:00
Chris Lattner
743a36c818
Implement a way of expanding shifts. This applies to targets that offer
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select operations or to shifts that are by a constant. This automatically
implements (with no special code) all of the special cases for shift by 32,
shift by < 32 and shift by > 32.
llvm-svn: 19679
2005-01-19 04:19:40 +00:00
Chris Lattner
0df1935505
Zero is cheaper than sign extend.
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llvm-svn: 19675
2005-01-18 21:57:59 +00:00
Chris Lattner
4360871e16
Fix some fixmes (promoting bools for select and brcond), fix promotion
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of zero and sign extends.
llvm-svn: 19671
2005-01-18 19:27:06 +00:00
Chris Lattner
eea485de1f
Keep track of the retval type as well.
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llvm-svn: 19670
2005-01-18 19:26:36 +00:00
Chris Lattner
ff086f3016
Teach legalize to promote copy(from|to)reg, instead of making the isel pass
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do it. This results in better code on X86 for floats (because if strict
precision is not required, we can elide some more expensive double -> float
conversions like the old isel did), and allows other targets to emit
CopyFromRegs that are not legal for arguments.
llvm-svn: 19668
2005-01-18 17:54:55 +00:00
Chris Lattner
891aa537f7
Teach legalize to promote SetCC results.
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llvm-svn: 19657
2005-01-18 02:59:52 +00:00
Chris Lattner
95307053ec
Allow setcc operations to have nonbool types.
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llvm-svn: 19656
2005-01-18 02:52:03 +00:00
Chris Lattner
906541da95
Fix the completely broken FP constant folds for setcc's.
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llvm-svn: 19651
2005-01-18 02:11:55 +00:00
Chris Lattner
c0aca0d13c
Non-volatile loads can be freely reordered against each other. This fixes
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X86/reg-pressure.ll again, and allows us to do nice things in other cases.
For example, we now codegen this sort of thing:
int %loadload(int *%X, int* %Y) {
%Z = load int* %Y
%Y = load int* %X ;; load between %Z and store
%Q = add int %Z, 1
store int %Q, int* %Y
ret int %Y
}
Into this:
loadload:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EAX, DWORD PTR [%EAX]
mov %ECX, DWORD PTR [%ESP + 8]
inc DWORD PTR [%ECX]
ret
where we weren't able to form the 'inc [mem]' before. This also lets the
instruction selector emit loads in any order it wants to, which can be good
for register pressure as well.
llvm-svn: 19644
2005-01-17 22:19:26 +00:00
Chris Lattner
49291c4d96
Don't call SelectionDAG.getRoot() directly, go through a forwarding method.
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llvm-svn: 19642
2005-01-17 19:43:36 +00:00