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57250eff2a
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20925 Commits

Author SHA1 Message Date
Akira Hatanaka
57250eff2a Reserve hardware registers. 
llvm-svn: 153486
 2012-03-27 00:40:56 +00:00
Evan Cheng
72cf12e416 ARM has a peephole optimization which looks for a def / use pair. The def 
produces a 32-bit immediate which is consumed by the use. It tries to 
fold the immediate by breaking it into two parts and fold them into the
immmediate fields of two uses. e.g
       movw    r2, #40885
       movt    r3, #46540
       add     r0, r0, r3
=>
       add.w   r0, r0, #3019898880
       add.w   r0, r0, #30146560
;
However, this transformation is incorrect if the user produces a flag. e.g.
       movw    r2, #40885
       movt    r3, #46540
       adds    r0, r0, r3
=>
       add.w   r0, r0, #3019898880
       adds.w  r0, r0, #30146560
Note the adds.w may not set the carry flag even if the original sequence
would.

rdar://11116189

llvm-svn: 153484
 2012-03-26 23:31:00 +00:00
Craig Topper
76f7896f49 Prune some includes and forward declarations. 
llvm-svn: 153429
 2012-03-26 06:58:25 +00:00
Craig Topper
bdc6d71a24 Prune includes and replace uses of ARMRegisterInfo.h with ARMBaeRegisterInfo.h 
llvm-svn: 153422
 2012-03-26 00:45:15 +00:00
Craig Topper
519813bca2 Replace uses of ARMBaseInstrInfo and ARMTargetMachine with the Base versions. 
llvm-svn: 153421
 2012-03-25 23:49:58 +00:00
Craig Topper
95a56ca1da Prune some includes and forward declarations. 
llvm-svn: 153415
 2012-03-25 18:10:17 +00:00
Hal Finkel
30d4df9f6d Fix small-integer VAARG on SVR4 ABI PPC64. 
The PPC64 SVR4 ABI requires integer stack arguments, and thus the var. args., that
are smaller than 64 bits be zero extended to 64 bits.

llvm-svn: 153373
 2012-03-24 03:53:55 +00:00
Justin Holewinski
715c9b53b3 PTX: Fix predicate logic bug 
Code such as:

%vreg100 = setcc %vreg10, -1, SETNE
brcond %vreg10, %tgt

was being incorrectly morphed into

%vreg100 = and %vreg10, 1
brcond %vreg10, %tgt

where the 'and' instruction could be eliminated since
such logic is on 1-bit types in the PTX back-end, leaving
us with just:

brcond %vreg10, %tgt

which essentially gives us inverted branch conditions.

llvm-svn: 153364
 2012-03-24 01:23:20 +00:00
Jim Grosbach
aefb0f06a9 ARM tidy up ARMConstantIsland.cpp. 
No functional change, just tidy up the code and nomenclature a bit.

llvm-svn: 153347
 2012-03-23 23:07:03 +00:00
Benjamin Kramer
a41ae12bd5 Include cstdio in a few place that depended on getting it transitively through StringExtras.h 
llvm-svn: 153328
 2012-03-23 11:35:30 +00:00
Benjamin Kramer
01e4003c0f Move ftostr into its last user (cppbackend) and simplify it a bit. 
New code should use raw_ostream.

llvm-svn: 153326
 2012-03-23 11:26:29 +00:00
Eric Christopher
3839c1ffd3 Remove the C backend. 
llvm-svn: 153307
 2012-03-23 05:50:46 +00:00
Silviu Baranga
d197baa066 Added soft fail checks for the disassembler when decoding some corner cases of the STRD, STRH, LDRD, LDRH, LDRSH and LDRSB instructions on ARM. 
llvm-svn: 153252
 2012-03-22 14:14:49 +00:00
Silviu Baranga
7bdfb9e34d Added soft fail cases for the disassembler when decoding LDRSBT, LDRHT or LDRSHT instruction on ARM 
llvm-svn: 153251
 2012-03-22 13:24:43 +00:00
Silviu Baranga
c03971d4b1 Added soft fail cases for the disassembler when decoding MUL instructions on ARM. 
llvm-svn: 153250
 2012-03-22 13:14:39 +00:00
Craig Topper
a2a674effc Remove some unnecessary forward declarations. 
llvm-svn: 153245
 2012-03-22 06:52:14 +00:00
Hal Finkel
84b247a2ef PPC::DBG_VALUE must use Reg+Imm frame-index elimination even for large offsets. Fixes PR12203. 
I don't have a small test case yet, but I'll try to construct one.

llvm-svn: 153240
 2012-03-22 05:28:19 +00:00
Kevin Enderby
e64335b34a Fix ARM disassembly of VST1 and VST2 instructions with writeback. And add test 
case for all opcodes handed by DecodeVSTInstruction() in ARMDisassembler.cpp .

llvm-svn: 153218
 2012-03-21 20:54:32 +00:00
Joerg Sonnenberger
4df2738e5f Put Is64BitMemOperand into !defined(NDEBUG) for now. 
llvm-svn: 153185
 2012-03-21 14:09:26 +00:00
Benjamin Kramer
ad9527ea4c Use a signed value for this enum to avoid spuriuos warnings from gcc. 
llvm-svn: 153184
 2012-03-21 13:48:11 +00:00
Joerg Sonnenberger
82af1c8704 Fix generation of the address size override prefix. Add assertions for 
the invalid cases. At least 16bit operand in 64bit mode is currently not
rejected in the parser.

llvm-svn: 153166
 2012-03-21 05:48:07 +00:00
Craig Topper
ee63bb1ffd Add typecast to silence -Wswitch warning introduced by r153153. 
llvm-svn: 153155
 2012-03-21 02:28:53 +00:00
Craig Topper
32b2c8fecc Spacing fixes and using 'unsigned' instead of 'int' to index to select shuffle elements for consistency with other shuffle code in X86 backend. 
llvm-svn: 153154
 2012-03-21 02:14:01 +00:00
Akira Hatanaka
cfaddf5c18 Incremental big endian patch by Jack Carter. 
These changes allow us to compile big endian from the command line for 32 bit
Mips targets. This patch will result in code and data actually being produced
in the correct endianess.

llvm-svn: 153153
 2012-03-21 00:52:01 +00:00
Chad Rosier
17f25ea47b [avx] Add patterns for combining vextractf128 + vmovaps/vmovups/vmobdqu to 
vextractf128 with 128-bit mem dest.

Combines

	vextractf128 $0, %ymm0, %xmm0
	vmovaps %xmm0, (%rdi)

to

    vextractf128 $0, %ymm0, (%rdi)

rdar://11082570

llvm-svn: 153139
 2012-03-20 21:43:40 +00:00
Evan Cheng
4dfb298aac Change conditional instructions definitions, e.g. ANDCC, ARMPseudoExpand and t2PseudoExpand. 
llvm-svn: 153135
 2012-03-20 21:28:05 +00:00
Matt Beaumont-Gay
0702af872e remove unused variable 
llvm-svn: 153116
 2012-03-20 19:52:05 +00:00
Chad Rosier
f6d522341c [avx] Add the AddedComplexity to the VINSERTI128 avx2 patterns to give 
precedence over the VINSERTF128 avx1 patterns.

llvm-svn: 153114
 2012-03-20 19:45:07 +00:00
Bob Wilson
52b3ad9532 Require a base pointer for stack realignment when SP may vary dynamically. 
ARMBaseRegisterInfo::canRealignStack was checking for variable-sized objects
but not for stack adjustments around calls.  Use hasReservedCallFrame() to
check for both.  The hasBasePointer function was already correctly checking
both conditions, so the effect of this was that a base pointer would be used
without checking whether the base pointer register could be reserved. I don't
have a small testcase for this.

<rdar://problem/11075906>

llvm-svn: 153110
 2012-03-20 19:28:25 +00:00
Bob Wilson
4fb4d4c6e0 Remove some redundant checks. 
ARMFrameLowering::hasReservedCallFrame is already checking for variable
sized objects, so there's no point in checking it twice.

llvm-svn: 153109
 2012-03-20 19:28:22 +00:00
Chad Rosier
73d8191b27 Whitespace. 
llvm-svn: 153105
 2012-03-20 18:38:33 +00:00
Chad Rosier
ffd2dbd676 [avx] Move the vextractf128 patterns closer to the vextractf128 def. Remove 
whitespace from test case.  No functional change intended.

llvm-svn: 153103
 2012-03-20 18:24:55 +00:00
Kevin Enderby
b87e1e0bfd Fix assembling ARM vst2 instructions with double-spaced registers. 
llvm-svn: 153099
 2012-03-20 17:41:51 +00:00
Jim Grosbach
b562c4f2fa ARM non-scattered MachO relocations for movw/movt. 
Needed when building -mdynamic-no-pic code.

rdar://10459256

llvm-svn: 153097
 2012-03-20 17:25:45 +00:00
Chad Rosier
143f33dc92 [avx] Adjust the VINSERTF128rm pattern to allow for unaligned loads. 
This results in things such as

	vmovups	16(%rdi), %xmm0
	vinsertf128	$1, %xmm0, %ymm0, %ymm0

to be combined to

    vinsertf128	$1, 16(%rdi), %ymm0, %ymm0

rdar://11076953

llvm-svn: 153092
 2012-03-20 17:08:51 +00:00
Silviu Baranga
d20ed770e5 The ARM instructions that have an unpredictable behavior when the pc register operand is given now fail with soft fail. Modified the regression tests to reflect this. 
llvm-svn: 153089
 2012-03-20 15:54:56 +00:00
Richard Barton
25f44c807b Test Commit - add a newline 
llvm-svn: 153083
 2012-03-20 10:50:35 +00:00
Craig Topper
61aa773498 Remove code that prevented lowering shuffles if they are used by load and themselves used by a extract_vector_elt. This was done to allow the DAG combiner to collapse to a single element load. Unfortunately, sometimes the extract_vector_elt would disappear before DAG combine could do the transformation leaving a vector_shuffle that isel couldn't handle. New code lets the shuffle be converted to a target specific node, but then adds a combine routine that can convert target specific nodes back to vector_shuffles if the folding criteria are met. 
llvm-svn: 153080
 2012-03-20 07:17:59 +00:00
Craig Topper
de938c64eb Factor out target shuffle mask decoding from getShuffleScalarElt and use a SmallVector of int instead of unsigned for shuffle mask in decode functions. Preparation for another change. 
llvm-svn: 153079
 2012-03-20 06:42:26 +00:00
Chris Lattner
9d0338734a fix a build failure with libc++ 
llvm-svn: 153063
 2012-03-19 23:31:01 +00:00
Jim Grosbach
0ca6b4a15d ARM branch relaxation for unconditional t1 branches. 
rdar://11059157

llvm-svn: 153055
 2012-03-19 21:32:32 +00:00
Jim Grosbach
65c7d4dab9 ARM assembly, accept optional '#' on lane index number. 
rdar://11057160

llvm-svn: 153053
 2012-03-19 20:39:53 +00:00
Anton Korobeynikov
ccc669ff8f Perform mul combine when multiplying wiht negative constants. 
Patch by Weiming Zhao!
This fixes PR12212

llvm-svn: 153049
 2012-03-19 19:19:50 +00:00
Preston Gurd
d1ae391210 This patch adds X86 instruction itineraries for non-pseudo opcodes in 
X86InstrCompiler.td.
 
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.

llvm-svn: 153033
 2012-03-19 14:10:12 +00:00
Benjamin Kramer
080ccc13a6 Add a note for -ffast-math optimization of vector norm. 
llvm-svn: 153031
 2012-03-19 00:43:34 +00:00
Craig Topper
34891f519c isCommutedMOVLMask should only look at 128-bit vectors to match isMOVLMask. 
llvm-svn: 153027
 2012-03-18 22:50:10 +00:00
Craig Topper
b1f171a213 Reorder includes in Target backends to following coding standards. Remove some superfluous forward declarations. 
llvm-svn: 152997
 2012-03-17 18:46:09 +00:00
Craig Topper
bb72c24507 Fix some copy and paste remnants of Cell and SPU in Hexagon files. 
llvm-svn: 152981
 2012-03-17 09:39:20 +00:00
Craig Topper
41786f284d Fix typo in file header. 
llvm-svn: 152980
 2012-03-17 09:28:37 +00:00
Craig Topper
3d39a3e5ba Pass TargetOptions to HexagonTargetMachine constructor by reference to match other targets and the base class. 
llvm-svn: 152979
 2012-03-17 09:24:09 +00:00