RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-20 11:33:24 +02:00
Code Issues Projects Releases Wiki Activity
18,021 Commits 4 Branches 5 Tags 704 MiB
57ea4daa2e
Commit Graph

53 Commits

Author SHA1 Message Date
Nate Begeman
402c04ff16 Set shift amount to Extend 
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions

llvm-svn: 21018
 2005-04-02 05:59:34 +00:00
Nate Begeman
d5d90ec76b Implement SetCC, fix ZERO_EXTEND_INREG 
llvm-svn: 20933
 2005-03-29 21:54:38 +00:00
Nate Begeman
32d1caae6d Remove fake instruction 'subc' (mnemonic for subfc). 
More pattern isel updates

llvm-svn: 20902
 2005-03-28 22:28:37 +00:00
Chris Lattner
5174b9cb60 Fix a problem where the PPC backend lost track of the fact that it had 
to save and restore the LR register on entry and exit of a leaf function
that needed to access globals or the constant pool.  This should hopefully
fix oscar from sending the PPC tester spinning out of control.

llvm-svn: 20197
 2005-02-15 20:26:49 +00:00
Chris Lattner
a0561d43b2 Factor out common .td file chunks. 
llvm-svn: 18982
 2004-12-16 16:31:57 +00:00
Chris Lattner
1f6882a401 Fix encoding of fneg instruction 
llvm-svn: 18226
 2004-11-25 03:53:44 +00:00
Nate Begeman
f8b9f49dc8 Fix encoding of bctrl, and remove some unused instructions 
llvm-svn: 18192
 2004-11-24 00:16:37 +00:00
Chris Lattner
f50b42adc1 Fix encoding of blr and bctr 
llvm-svn: 18178
 2004-11-23 22:06:24 +00:00
Chris Lattner
512b1d6c2a Fix encodings 
llvm-svn: 18164
 2004-11-23 19:23:18 +00:00
Chris Lattner
1b163867c6 LA is really addi. Be consistent with operand ordering to avoid confusing the code emitter 
llvm-svn: 18138
 2004-11-23 05:54:25 +00:00
Chris Lattner
5b68bdb2ce Comment out a couple of unused instructions. 
llvm-svn: 18135
 2004-11-22 23:07:01 +00:00
Misha Brukman
757502af07 Add BCTR and LWZU instruction opcodes 
llvm-svn: 17851
 2004-11-15 21:20:09 +00:00
Misha Brukman
58d9e43fa1 Add BA, BL, and BLA opcodes 
llvm-svn: 17193
 2004-10-23 20:29:24 +00:00
Misha Brukman
e4ae05e099 Fix the SPR field for MTLR, MFLR, MTCTR, and MFCTR instructions. 
The decimal value given in the manual (8 or 9) really needs to be multiplied by
a factor of 32 because of the group of 5 zero bits after the register code.

llvm-svn: 17182
 2004-10-23 06:05:49 +00:00
Misha Brukman
5cea06807d The value of the XO field for MFLR and MFCTR is 339, not 399 
llvm-svn: 17181
 2004-10-23 05:38:55 +00:00
Nate Begeman
d4c970aa3d Finally fix one of the oldest FIXMEs in the PowerPC backend: correctly 
flag rotate left word immediate then mask insert (rlwimi) as a two-address
instruction, and update the ISel usage of the instruction accordingly.

This will allow us to properly schedule rlwimi, and use it to efficiently
codegen bitfield operations.

llvm-svn: 17068
 2004-10-16 20:43:38 +00:00
Nate Begeman
370b1b7a9a Several fixes and enhancements to the PPC32 backend. 
1. Fix an illegal argument to getClassB when deciding whether or not to
   sign extend a byte load.

2. Initial addition of isLoad and isStore flags to the instruction .td file
   for eventual use in a scheduler.

3. Rewrite of how constants are handled in emitSimpleBinaryOperation so
   that we can emit the PowerPC shifted immediate instructions far more
   often.  This allows us to emit the following code:

int foo(int x) { return x | 0x00F0000; }

_foo:
.LBB_foo_0:     ; entry
        ; IMPLICIT_DEF
        oris r3, r3, 15
        blr

llvm-svn: 16826
 2004-10-07 22:30:03 +00:00
Nate Begeman
61d1797c03 add optimized code sequences for setcc x, 0 
llvm-svn: 16478
 2004-09-22 04:40:25 +00:00
Nate Begeman
ce6d62eac7 Add 64 bit divide instructions, and use them 
llvm-svn: 16198
 2004-09-06 18:46:59 +00:00
Nate Begeman
e816600b3e All PPC instructions are now auto-printed 
32 and 64 bit AsmWriters unified
Darwin and AIX specific features of AsmWriter split out

llvm-svn: 16163
 2004-09-04 05:00:00 +00:00
Nate Begeman
3bad485eec Convert remaining X-Form and Pseudo instructions over to asm writer 
llvm-svn: 16142
 2004-09-02 08:13:00 +00:00
Nate Begeman
220175aa4d convert M and MD form instructions to generated asm writer 
llvm-svn: 16121
 2004-08-31 02:28:08 +00:00
Nate Begeman
e58512a61c Move yet more instructions over to being printed by the generated asm writer 
llvm-svn: 16112
 2004-08-30 02:28:06 +00:00
Nate Begeman
7792aa1f8b Convert A-Form instructions to auto-generated asm writer 
llvm-svn: 16107
 2004-08-29 22:45:13 +00:00
Nate Begeman
68e2dd66af Improvements to int->float cast code for PPC-64 
llvm-svn: 16105
 2004-08-29 22:02:43 +00:00
Nate Begeman
923af3763d Implement the following missing functionality in the PPC backend: 
cast fp->bool
cast ulong->fp
algebraic right shift long by non-constant value
These changes tested across most of the test suite.  Fixes Regression/casts

llvm-svn: 16081
 2004-08-29 08:19:32 +00:00
Nate Begeman
dd700ce5e4 Move XForm instructions over to the auto-generated asm writer 
llvm-svn: 15962
 2004-08-21 05:56:39 +00:00
Nate Begeman
2f68d05d47 Implement code to convert SetCC into straight line code where appropriate. Add necessary instructions for this transformation to the .td file. 
llvm-svn: 15952
 2004-08-20 09:56:22 +00:00
Nate Begeman
81c97654da Clean up floating point instruction selection. 
Change int->float cast code to put conversion constants in constant pool.
Shorten code sequence for constant pool fp loads.
Remove LOADLoDirect/LOADLoIndirect psuedo instructions and tweak asmwriter

llvm-svn: 15913
 2004-08-19 05:20:54 +00:00
Chris Lattner
6ddb5d6c76 Convert all of the DForm_6* operations, which makes all of the Zimm16 users 
dead.

llvm-svn: 15754
 2004-08-15 05:46:14 +00:00
Chris Lattner
41839ea5cd Convert the DForm_4 over to the asmprintergen 
llvm-svn: 15751
 2004-08-15 05:20:16 +00:00
Chris Lattner
e19e10e800 Print mflr using the asmwriter generator 
llvm-svn: 15749
 2004-08-14 23:27:29 +00:00
Nate Begeman
557f61c4d6 Add indexed forms of load doubleword and load word algebraic for 64 bit targets 
llvm-svn: 15743
 2004-08-14 22:12:20 +00:00
Nate Begeman
48359fbcd0 Add some more 64 bit instructions we need for the PowerPC-64 ISel to the tablegen files 
llvm-svn: 15710
 2004-08-13 02:19:26 +00:00
Misha Brukman
0b67e02e9c Fix names of 64-bit CMP*D* opcodes, add LWA and STD* opcodes 
llvm-svn: 15668
 2004-08-11 23:33:34 +00:00
Misha Brukman
08b8a09113 Add support for 64-bit CMPDI, CMPLDI, and CMPLD opcodes 
llvm-svn: 15667
 2004-08-11 20:56:14 +00:00
Misha Brukman
7325a6c790 Add doubleword load/store (64-bit only). 
llvm-svn: 15665
 2004-08-11 15:54:36 +00:00
Nate Begeman
b74ee41754 Fix casts of float to unsigned long 
Replace STDX (store 64 bit int indexed) with STFDX (store double indexed)
Fix latent bug in indexed load generation
Generate indexed loads and stores in many more cases

llvm-svn: 15626
 2004-08-10 20:42:36 +00:00
Misha Brukman
ba013330a8 Use instruction formats as defined in the PowerPC ISA manual 
llvm-svn: 15577
 2004-08-09 17:24:04 +00:00
Misha Brukman
07f8b33325 Remove unused opcodes. 
llvm-svn: 15447
 2004-08-03 20:23:44 +00:00
Misha Brukman
10a585beaf * Use simpler instruction templates to define instructions 
* Fix several extended opcodes

llvm-svn: 15423
 2004-08-02 21:58:52 +00:00
Misha Brukman
f2119a5b6f Separate instruction formats from instruction definitions. 
llvm-svn: 15414
 2004-08-02 16:54:54 +00:00
Misha Brukman
148ad01de1 Renamed files: 
* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td

llvm-svn: 15295
 2004-07-27 23:29:16 +00:00
Misha Brukman
8c047d4fad Add COND_BRANCH pseudo instruction, patch by Nate Begeman. 
llvm-svn: 15283
 2004-07-27 18:35:54 +00:00
Misha Brukman
93b0ea58a2 MovePCtoLR (which is `bl' in disguise) modifies LR implicitly 
llvm-svn: 15272
 2004-07-27 17:15:05 +00:00
Misha Brukman
3d395cbda3 Add SUBI instruction 
llvm-svn: 15077
 2004-07-21 15:53:04 +00:00
Misha Brukman
f47940855d Differentiate between global and weak symbol loads 
llvm-svn: 15037
 2004-07-20 15:52:25 +00:00
Misha Brukman
f93e5532d5 Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman 
llvm-svn: 14895
 2004-07-16 20:33:41 +00:00
Misha Brukman
efcb6b8c2c * Coalesce the handy CALL* alias opcodes with the standard ones 
* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls

llvm-svn: 14511
 2004-06-30 22:00:45 +00:00
Misha Brukman
2242e8d27f * Use LA instead of LWZ for LoadLoAddr 
* Specify the isCall bit and caller-save registers for some call instrs

llvm-svn: 14501
 2004-06-29 23:37:36 +00:00