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Author SHA1 Message Date
Matt Arsenault
cf419f3ccc DAGCombiner: Turn truncate of a bitcasted vector to an extract 
On AMDGPU where operations i64 operations are often bitcasted to v2i32
and back, this pattern shows up regularly where it breaks some
expected combines on i64, such as load width reducing.

This fixes some test failures in a future commit when i64 loads
are changed to promote.

llvm-svn: 262397
 2016-03-01 21:31:53 +00:00