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Commit Graph

19047 Commits

Author SHA1 Message Date
Nico Rieck
4acab3dcc9 Rename inst_range() to instructions() for consistency. NFC
llvm-svn: 244248
2015-08-06 19:10:45 +00:00
Kit Barton
5eb6e29fcf Fix possible infinite loop in shrink wrapping when searching for save/restore
points.

There is an infinite loop that can occur in Shrink Wrapping while searching 
for the Save/Restore points. 

Part of this search checks whether the save/restore points are located in
different loop nests and if so, uses the (post) dominator trees to find the
immediate (post) dominator blocks. However, if the current block does not have
any immediate (post) dominators then this search will result in an infinite
loop. This can occur in code containing an infinite loop.

The modification checks whether the immediate (post) dominator is different from
the current save/restore block. If it is not, then the search terminates and the
current location is not considered as a valid save/restore point for shrink wrapping.

Phabricator: http://reviews.llvm.org/D11607
llvm-svn: 244247
2015-08-06 19:01:57 +00:00
Alex Lorenz
8ecabffd63 MIR Parser: Report an error when parsing duplicate memory operand flags.
llvm-svn: 244240
2015-08-06 18:26:36 +00:00
Cong Hou
f7490fad1b Revert r244154 which causes some build failure. See https://llvm.org/bugs/show_bug.cgi?id=24377.
llvm-svn: 244239
2015-08-06 18:17:29 +00:00
Kit Barton
05694fa00a This patch changes the interface to enable the shrink wrapping optimization.
It adds a new constructor, which takes a std::function predicate function that
is run at the beginning of shrink wrapping to determine whether the optimization
should run on the given machine function. The std::function can be overridden by
each target, allowing target-specific decisions to be made on each machine
function.

This is necessary for PowerPC, as the decision to run shrink wrapping is
partially based on the ABI. Futhermore, this operates nicely with the GCC iFunc
capability, which allows option overrides on a per-function basis.

Phabricator: http://reviews.llvm.org/D11421
llvm-svn: 244235
2015-08-06 18:02:53 +00:00
Alex Lorenz
0d1da50e29 MIR Serialization: Serialize the 'invariant' machine memory operand flag.
llvm-svn: 244230
2015-08-06 16:55:53 +00:00
Richard Diamond
eb6992a477 Fix an alignment error in llvm::expandAtomicRMWToCmpXchg without breaking the build where X86 isn't enabled.
Summary: Divide the primitive size in bits by eight so the initial load's alignment is in bytes as expected. Tested with the included unit test.

Reviewers: rengolin, jfb

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11804

llvm-svn: 244229
2015-08-06 16:55:03 +00:00
Alex Lorenz
b105a060cc MIR Serialization: Serialize the 'non-temporal' machine memory operand flag.
llvm-svn: 244228
2015-08-06 16:49:30 +00:00
Renato Golin
d87c97f34a Revert "Divide the primitive size in bits by eight so the initial load's alignment is in bytes as expected. Tested with the included unit test."
This reverts commit r244155, as it was breaking the buildbots for too long.
Should be reapplied with proper fix.

llvm-svn: 244205
2015-08-06 10:37:59 +00:00
Chandler Carruth
a0655c50ee [PM/AA] Hoist the interface for BasicAA into a header file.
This is the first mechanical step in preparation for making this and all
the other alias analysis passes available to the new pass manager. I'm
factoring out all the totally boring changes I can so I'm moving code
around here with no other changes. I've even minimized the formatting
churn.

I'll reformat and freshen comments on the interface now that its located
in the right place so that the substantive changes don't triger this.

llvm-svn: 244197
2015-08-06 07:33:15 +00:00
Chandler Carruth
595690977b [PM/AA] Simplify the AliasAnalysis interface by removing a wrapper
around a DataLayout interface in favor of directly querying DataLayout.

This wrapper specifically helped handle the case where this no
DataLayout, but LLVM now requires it simplifynig all of this. I've
updated callers to directly query DataLayout. This in turn exposed
a bunch of places where we should have DataLayout readily available but
don't which I've fixed. This then in turn exposed that we were passing
DataLayout around in a bunch of arguments rather than making it readily
available so I've also fixed that.

No functionality changed.

llvm-svn: 244189
2015-08-06 02:05:46 +00:00
Alex Lorenz
b06d114835 MIR Serialization: Initial serialization of the machine operand target flags.
This commit implements the initial serialization of the machine operand target
flags. It extends the 'TargetInstrInfo' class to add two new methods that help
to provide text based serialization for the target flags.

This commit can serialize only the X86 target flags, and the target flags for
the other targets will be serialized in the follow-up commits.

Reviewers: Duncan P. N. Exon Smith
llvm-svn: 244185
2015-08-06 00:44:07 +00:00
Reid Kleckner
f884663717 If the "CodeView" module flag is set, emit codeview instead of DWARF
Summary:
Emit both DWARF and CodeView if "CodeView" and "Dwarf Version" module
flags are set.

Reviewers: majnemer

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11756

llvm-svn: 244158
2015-08-05 22:26:20 +00:00
Alex Lorenz
3768a6786c MIR Serialization: Serialize the machine operand's offset.
This commit serializes the offset for the following operands: target index,
global address, external symbol, constant pool index, and block address.

llvm-svn: 244157
2015-08-05 22:26:15 +00:00
Richard Diamond
688e7b03a7 Divide the primitive size in bits by eight so the initial load's alignment is in
bytes as expected. Tested with the included unit test.

llvm-svn: 244155
2015-08-05 22:10:57 +00:00
Cong Hou
26ec441a7b Record whether the weights on out-edges from a MBB are normalized.
1. Create a utility function normalizeEdgeWeights() in MachineBranchProbabilityInfo that normalizes a list of edge weights so that the sum of then can fit in uint32_t.
2. Provide an interface in MachineBasicBlock to normalize its successors' weights.
3. Add a flag in MachineBasicBlock that tracks whether its successors' weights are normalized.
4. Provide an overload of getSumForBlock that accepts a non-const pointer to a MBB so that it can force normalizing this MBB's successors' weights.
5. Update several uses of getSumForBlock() by eliminating the once needed weight scale.

Differential Revision: http://reviews.llvm.org/D11442

llvm-svn: 244154
2015-08-05 22:01:20 +00:00
JF Bastien
cf4a8a3579 Revert "Fix MO's analyzePhysReg, it was confusing sub- and super-registers. Problem pointed out by Michael Hordijk."
I mistakenly committed the patch for D6629, and was trying to commit another. Reverting until it gets proper signoff.

llvm-svn: 244121
2015-08-05 20:53:56 +00:00
JF Bastien
e3b11e6e69 Fix MO's analyzePhysReg, it was confusing sub- and super-registers. Problem pointed out by Michael Hordijk.
llvm-svn: 244120
2015-08-05 20:49:46 +00:00
Richard Diamond
ef0da0e1d6 Write access test.
llvm-svn: 244103
2015-08-05 19:40:39 +00:00
Alex Lorenz
f8bf4abe0d MIR Parser: Report an error when parsing large immediate operands.
llvm-svn: 244100
2015-08-05 19:03:42 +00:00
Alex Lorenz
8fc56ec7f9 MIR Serialization: Serialize the typed immediate integer machine operands.
llvm-svn: 244098
2015-08-05 18:52:21 +00:00
Alex Lorenz
8e16648112 MIR Parser: Extract the IR constant parsing code into a new method. NFC.
This commit extracts the code that parses the IR constant values into a new
method named 'parseIRConstant' in the 'MIParser' class. The new method will
be reused by the code that parses the typed integer immediate machine operands.

llvm-svn: 244093
2015-08-05 18:44:00 +00:00
Alex Lorenz
32764a9d0f MIR Parser: Report an error when parsing duplicate register flags.
llvm-svn: 244081
2015-08-05 18:09:03 +00:00
Chandler Carruth
98500f2974 [TTI] Make the cost APIs in TargetTransformInfo consistently use 'int'
rather than 'unsigned' for their costs.

For something like costs in particular there is a natural "negative"
value, that of savings or saved cost. As a consequence, there is a lot
of code that subtracts or creates negative values based on cost, all of
which is prone to awkwardness or bugs when dealing with an unsigned
type. Similarly, we *never* want these values to wrap, as that would
cause Very Bad code generation (likely percieved as an infinite loop as
we try to emit over 2^32 instructions or some such insanity).

All around 'int' seems a much better fit for these basic metrics. I've
added asserts to ensure that at least the TTI interface never returns
negative numbers here. If we ever have a use case for negative numbers,
we can remove this, but this way a bug where someone used '-1' to
produce a 'very large' cost will be caught by the assert.

This passes all tests, and is also UBSan clean.

No functional change intended.

Differential Revision: http://reviews.llvm.org/D11741

llvm-svn: 244080
2015-08-05 18:08:10 +00:00
Alex Lorenz
6b0071372b MIR Serialization: Serialize the 'early-clobber' register operand flag.
llvm-svn: 244075
2015-08-05 17:49:03 +00:00
Alex Lorenz
5058149b87 MIR Serialization: Serialize the 'debug-use' register operand flag.
llvm-svn: 244071
2015-08-05 17:41:17 +00:00
Alex Lorenz
aab548425e MIR Parser: Simplify the handling of quoted tokens. NFC.
The machine instructions lexer should not expose the difference between quoted
and unquoted tokens to the parser.

llvm-svn: 244068
2015-08-05 17:35:55 +00:00
Sanjay Patel
ac82517d0a revert r243687: enable fast-math-flag propagation to DAG nodes
We can't propagate FMF partially without breaking DAG-level CSE. We either need to
relax CSE to account for mismatched FMF as a temporary work-around or fully propagate
FMF throughout the DAG.

Surprisingly, there are no existing regression tests for this, but here's an example:

  define float @fmf(float %a, float %b) {
    %mul1 = fmul fast float %a, %b
    %nega = fsub fast float 0.0, %a
    %mul2 = fmul fast float %nega, %b
    %abx2 = fsub fast float %mul1, %mul2
    ret float %abx2
  }


$ llc -o - badflags.ll -march=x86-64 -mattr=fma -enable-unsafe-fp-math -enable-fmf-dag=0
...
    vmulss    %xmm1, %xmm0, %xmm0
    vaddss    %xmm0, %xmm0, %xmm0
    retq

$ llc -o - badflags.ll -march=x86-64 -mattr=fma -enable-unsafe-fp-math -enable-fmf-dag=1
...
    vmulss    %xmm1, %xmm0, %xmm2
    vfmadd213ss    %xmm2, %xmm1, %xmm0  <--- failed to recognize that (a * b) was already calculated
    retq

llvm-svn: 244053
2015-08-05 15:12:03 +00:00
Hal Finkel
58e66c2716 [MachineCombiner] Don't use the opcode-only form of computeInstrLatency
In r242277, I updated the MachineCombiner to work with itineraries, but I
missed a call that is scheduling-model-only (the opcode-only form of
computeInstrLatency). Using the form that takes an MI* allows this to work with
itineraries (and should be NFC for subtargets with scheduling models).

llvm-svn: 244020
2015-08-05 07:45:28 +00:00
Sanjay Patel
83e1c48540 wrap OptSize and MinSize attributes for easier and consistent access (NFCI)
Create wrapper methods in the Function class for the OptimizeForSize and MinSize
attributes. We want to hide the logic of "or'ing" them together when optimizing
just for size (-Os).

Currently, we are not consistent about this and rely on a front-end to always set
OptimizeForSize (-Os) if MinSize (-Oz) is on. Thus, there are 18 FIXME changes here
that should be added as follow-on patches with regression tests.

This patch is NFC-intended: it just replaces existing direct accesses of the attributes
by the equivalent wrapper call.

Differential Revision: http://reviews.llvm.org/D11734

llvm-svn: 243994
2015-08-04 15:49:57 +00:00
Hal Finkel
0942a1c9ca [SDAG] Fix a result chain in ExpandUnalignedLoad
On the code path in ExpandUnalignedLoad which expands an unaligned vector/fp
value in terms of a legal integer load of the same size, the ChainResult needs
to be the chain result of the integer load.

No in-tree test case is currently available.

Patch by Jan Hranac!

llvm-svn: 243956
2015-08-04 06:29:12 +00:00
Chen Li
d484b66994 Introduce enum value for previously defined metadata -- make.implicit
Summary: This patch adds enum value for an existing metadata type -- make.implicit. Using preassigned enum will be helpful to get compile time type checking and avoid string construction and comparison. The patch also changes uses of make.implicit from string metadata to enum metadata. There is no functionality change.

Reviewers: reames

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11698

llvm-svn: 243954
2015-08-04 04:41:34 +00:00
Ahmed Bougacha
4da2acb3ed [CodeGen] Fix FCOPYSIGN legalization to account for mismatched types.
We used to legalize it like it's any other binary operations.  It's not,
because it accepts mismatched operand types.  Because of that, we used
to hit various asserts and miscompiles.

Specialize vector legalizations to, in the worst case, unroll, or, when
possible, to just legalize the operand that needs legalization.

Scalarization isn't covered, because I can't think of a target where
some but not all of the 1-element vector types are to be scalarized.

llvm-svn: 243924
2015-08-04 00:32:55 +00:00
Alex Lorenz
076303e68c MIR Serialization: Serialize the 'volatile' machine memory operand flag.
llvm-svn: 243923
2015-08-04 00:24:45 +00:00
Alex Lorenz
1167a86bcb MIR Serialization: Initial serialization of the machine memory operands.
Reviewers: Duncan P. N. Exon Smith
llvm-svn: 243915
2015-08-03 23:08:19 +00:00
David Blaikie
95e59129ca -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11
Various value handles needed to be copy constructible and copy
assignable (mostly for their use in DenseMap). But to avoid an API that
might allow accidental slicing, make these members protected in the base
class and make derived classes final (the special members become
implicitly public there - but disallowing further derived classes that
might be sliced to the intermediate type).

Might be worth having a warning a bit like -Wnon-virtual-dtor that
catches public move/copy assign/ctors in classes with virtual functions.
(suppressable in the same way - by making them protected in the base,
and making the derived classes final) Could be fancier and only diagnose
them when they're actually called, potentially.

Also allow a few default implementations where custom implementations
(especially with non-standard return types) were implemented.

llvm-svn: 243909
2015-08-03 22:30:24 +00:00
David Blaikie
b591224920 -Wdeprecated-clean: Fix cases of violating the rule of 5 in ways that are deprecated in C++11
Some functions return concrete ByteStreamers by value - explicitly
support that in the base class. (dtor can be virtual, no one seems to be
polymorphically owning/destroying them)

llvm-svn: 243897
2015-08-03 20:12:58 +00:00
JF Bastien
e43a24e432 Refactor AtomicExpand::expandAtomicRMWToCmpXchg into a standalone function.
Summary:
This is useful for PNaCl's `RewriteAtomics` pass. NaCl intrinsics don't exist for some of the more exotic RMW instructions, so by refactoring this function into its own, `RewriteAtomics` can share code rewriting those atomics with `AtomicExpand` while additionally saving a few cycles by generating the `cmpxchg` NaCl-specific intrinsic with the callback. Without this patch, `RewriteAtomics` would require two extra passes over functions, by first requiring use of the full `AtomicExpand` pass to just expand the leftover exotic RMWs and then running itself again to expand resulting `cmpxchg`s.

NFC

Reviewers: jfb

Subscribers: jfb, llvm-commits

Differential Revision: http://reviews.llvm.org/D11422

llvm-svn: 243880
2015-08-03 15:29:47 +00:00
John Brawn
bc90a464f4 [GlobalMerge] Allow targets to enable merging of extern variables, NFC.
Adjust the GlobalMergeOnExternal option so that the default behaviour is to
do whatever the Target thinks is best. Explicitly enabled or disabling the
option will override this default.

Differential Revision: http://reviews.llvm.org/D10965

llvm-svn: 243873
2015-08-03 12:08:41 +00:00
Duncan P. N. Exon Smith
b03262f421 AsmPrinter: Split out non-DIE printing from DIE::print(), NFC
Split out a helper `printValues()` for printing `DIEBlock` and `DIELoc`,
instead of relying on `DIE::print()`.  The shared code was actually
fairly small there.  No functionality change intended.

llvm-svn: 243856
2015-08-02 20:46:49 +00:00
Duncan P. N. Exon Smith
891fb97a9c AsmPrinter: Take DIEValueList in some DwarfUnit API, NFC
Take `DIEValueList` instead of `DIE` so that `DIEBlock` and `DIELoc` can
stop inheriting from `DIE` in a future commit.

llvm-svn: 243855
2015-08-02 20:44:46 +00:00
Duncan P. N. Exon Smith
c235ebc0da AsmPrinter: Change DIEValueList to a subclass of DIE, NFC
Rewrite `DIEValueList` as a subclass of `DIE`, renaming its API to match
`DIE`'s.  This is preparation for changing `DIEBlock` and `DIELoc` to
stop inheriting from `DIE` and inherit directly from `DIEValueList`.

I thought about leaving this as a has-a relationship (and changing
`DIELoc` and `DIEBlock` to also have-a `DIEValueList`), but that seemed
to require a fair bit more boilerplate and I think it needed more
changes to the `DwarfUnit` API than this will.

No functionality change intended here.

llvm-svn: 243854
2015-08-02 20:42:45 +00:00
Simon Pilgrim
a907c49a80 Remove trailing whitespace. NFCI.
llvm-svn: 243838
2015-08-01 17:06:47 +00:00
Simon Pilgrim
a79aa68f23 Use SDValue bool check. NFCI.
llvm-svn: 243837
2015-08-01 17:05:50 +00:00
Simon Pilgrim
67ccd7713f [DAGCombiner] Convert constant AND masks to shuffle clear masks down to the byte level
The XformToShuffleWithZero method currently checks AND masks at the per-lane level for all-one and all-zero constants and attempts to convert them to legal shuffle clear masks.

This patch generalises XformToShuffleWithZero, splitting and checking the sub-lanes of the constants down to the byte level to see if any legal shuffle clear masks are possible. This allows a lot of masks (often from legalization or truncation) to be folded into existing shuffle patterns and removes a lot of constant mask loading.

There are a few examples of poor shuffle lowering that are exposed by this patch that will be cleaned up in future patches (e.g. merging shuffles that are separated by bitcasts, x86 legalized v8i8 zero extension uses PMOVZX+AND+AND instead of AND+PMOVZX, etc.)

Differential Revision: http://reviews.llvm.org/D11518

llvm-svn: 243831
2015-08-01 10:01:46 +00:00
Alex Lorenz
36d3115a60 MIR Parser: Report an error when a jump table entry is redefined.
llvm-svn: 243798
2015-07-31 23:13:23 +00:00
Alex Lorenz
db0dfc201f MIR Parser: Remove unused variable.
This variable is unused as of r243572.

llvm-svn: 243796
2015-07-31 22:59:20 +00:00
Alex Lorenz
d7ba1eec00 MIR Serialization: Serialize the floating point immediate machine operands.
Reviewers: Duncan P. N. Exon Smith
llvm-svn: 243780
2015-07-31 20:49:21 +00:00
Duncan P. N. Exon Smith
08a36a35c8 DI: Remove DW_TAG_arg_variable and DW_TAG_auto_variable
Remove the fake `DW_TAG_auto_variable` and `DW_TAG_arg_variable` tags,
using `DW_TAG_variable` in their place Stop exposing the `tag:` field at
all in the assembly format for `DILocalVariable`.

Most of the testcase updates were generated by the following sed script:

    find test/ -name "*.ll" -o -name "*.mir" |
    xargs grep -l 'DILocalVariable' |
    xargs sed -i '' \
      -e 's/tag: DW_TAG_arg_variable, //' \
      -e 's/tag: DW_TAG_auto_variable, //'

There were only a handful of tests in `test/Assembly` that I needed to
update by hand.

(Note: a follow-up could change `DILocalVariable::DILocalVariable()` to
set the tag to `DW_TAG_formal_parameter` instead of `DW_TAG_variable`
(as appropriate), instead of having that logic magically in the backend
in `DbgVariable`.  I've added a FIXME to that effect.)

llvm-svn: 243774
2015-07-31 18:58:39 +00:00
David Majnemer
34ee3789f3 New EH representation for MSVC compatibility
This introduces new instructions neccessary to implement MSVC-compatible
exception handling support.  Most of the middle-end and none of the
back-end haven't been audited or updated to take them into account.

Differential Revision: http://reviews.llvm.org/D11097

llvm-svn: 243766
2015-07-31 17:58:14 +00:00