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15007 Commits

Author SHA1 Message Date
Jim Grosbach
1b102f0b63 Add ARM heuristic for when to allocate a virtual base register for stack 
access. rdar://8277890&7352504

llvm-svn: 111968
 2010-08-24 21:19:33 +00:00
Daniel Dunbar
b96b0c40d3 MC/X86: Tweak imul recognition, previous hack only applies for the imul form 
taking immediates.

llvm-svn: 111950
 2010-08-24 19:37:56 +00:00
Daniel Dunbar
3b74f75d13 MC/X86: Add custom hack for recognizing "imul $12, %eax" and friends. 
llvm-svn: 111947
 2010-08-24 19:24:18 +00:00
Daniel Dunbar
75e77b0063 MC/X86: Warn on scale factors > 1 without index register, instead of erroring, 
for 'as' compatibility.

llvm-svn: 111945
 2010-08-24 19:13:38 +00:00
Jim Grosbach
0c3eb7ca50 Move enabling the local stack allocation pass into the target where it belongs. 
For now it's still a command line option, but the interface to the generic
code doesn't need to know that.

llvm-svn: 111942
 2010-08-24 19:05:43 +00:00
Jim Grosbach
a110ecf96a add ARM cmd line option to force always using virtual base regs when possible. 
Intended to help ease reproducing problems by increasing base register usage
after heuristics for only using the when needed are in place.

llvm-svn: 111930
 2010-08-24 18:04:52 +00:00
Dan Gohman
e400c660e4 Fix X86's isLegalAddressingMode to recognize that static addresses 
need not be RIP-relative in small mode.

llvm-svn: 111917
 2010-08-24 15:55:12 +00:00
Kalle Raiskila
1be8a5f947 Fix SPU BE to use all the available return registers. 
llc used to assert on the added testcase.

llvm-svn: 111911
 2010-08-24 11:50:48 +00:00
Kalle Raiskila
ef9e592448 Remove some dead code from SPU BE that remained 
from 64bit vector support.

llvm-svn: 111910
 2010-08-24 11:05:51 +00:00
Bruno Cardoso Lopes
7939025262 Use pshufhw and pshuflw in more cases and fix getTargetShuffleNode number of arguments 
llvm-svn: 111890
 2010-08-24 01:16:15 +00:00
Bill Wendling
c92b4d86ad Add comments for what the condition code symbols mean. 
llvm-svn: 111889
 2010-08-24 01:11:30 +00:00
Eric Christopher
c2ed70d52b Update comment. 
llvm-svn: 111887
 2010-08-24 01:10:52 +00:00
Eric Christopher
5f3382bacc Fix the opcode and the operands for the load instruction. 
llvm-svn: 111885
 2010-08-24 01:10:04 +00:00
Eric Christopher
5d1289db95 Add register class hack that needs to go away, but makes it more obvious 
that it needs to go away.  Use loadRegFromStackSlot where possible.

Also, remember to update the value map.

llvm-svn: 111883
 2010-08-24 00:50:47 +00:00
Eric Christopher
696d6ee9d7 Add some more debugging code, make it more obvious that RegOffset is 
getting an address for an object and select some default values.

llvm-svn: 111871
 2010-08-24 00:07:24 +00:00
Eric Christopher
a1652c6ea6 Don't need the extra register here. 
llvm-svn: 111864
 2010-08-23 23:28:04 +00:00
Eric Christopher
2f01adebca Add some more "get address into register" code and a more TODOs/FIXMEs. 
llvm-svn: 111860
 2010-08-23 23:14:31 +00:00
Eric Christopher
7ec47db6b2 Add an ARMFunctionInfo member and use it. 
llvm-svn: 111854
 2010-08-23 22:32:45 +00:00
Eric Christopher
e0d09e27f8 Start getting ARM loads/address computation going. 
llvm-svn: 111850
 2010-08-23 21:44:12 +00:00
Bruno Cardoso Lopes
ed9ff8d8d0 Start using target speficic nodes for shuffles: pshufhw and pshuflw 
llvm-svn: 111837
 2010-08-23 20:41:02 +00:00
Gabor Greif
6bd4b1cc6c tyops 
llvm-svn: 111835
 2010-08-23 20:30:51 +00:00
Chris Lattner
f0f35c4aea Add a new llvm.x86.int intrinsic, allowing access to the 
x86 int and int3 instructions.  Patch by Peter Housel!

llvm-svn: 111831
 2010-08-23 19:39:25 +00:00
Chris Lattner
f4dfc7aaab random improvement for variable shift codegen. 
llvm-svn: 111813
 2010-08-23 17:30:29 +00:00
Anton Korobeynikov
a68e2a53a1 Revert invalid r111792. Jump tables are not broken on x86-64 / coff, 
it's COFF emitter which does not support differences of two symbols
(and needs to be fixed). GAS is pretty fine with code produced.

llvm-svn: 111801
 2010-08-23 07:38:51 +00:00
Michael J. Spencer
c52ac23659 Workaround broken jump tables on x86-64 COFF. 
llvm-svn: 111792
 2010-08-23 04:45:37 +00:00
Anton Korobeynikov
c3294e6abe Use rip-rel addressing on win64 by default. For this we just 
defaults to small pic code model.

llvm-svn: 111741
 2010-08-21 17:21:11 +00:00
Michael J. Spencer
18689045ce MC: Add partial x86-64 support to COFF. 
llvm-svn: 111728
 2010-08-21 05:58:13 +00:00
Dan Gohman
30b8e6cfd2 Fix x86 fast-isel's cmp+branch folding to avoid folding when the 
comparison is in a different basic block from the branch. In such
cases, the comparison's operands may not have initialized virtual
registers available.

llvm-svn: 111709
 2010-08-21 02:32:36 +00:00
Bruno Cardoso Lopes
1998fbbf1a Prepare LowerVECTOR_SHUFFLEv8i16 to use x86 target specific nodes directly 
llvm-svn: 111704
 2010-08-21 01:32:18 +00:00
Bruno Cardoso Lopes
28d9071635 This is the first step towards refactoring the x86 vector shuffle code. The 
general idea here is to have a group of x86 target specific nodes which are
going to be selected during lowering and then directly matched in isel.

The commit includes the addition of those specific nodes and a *bunch* of
patterns, and incrementally we're going to switch between them and what we
have right now. Both the patterns and target specific nodes can change as
we move forward with this work.

llvm-svn: 111691
 2010-08-20 22:55:05 +00:00
Bill Wendling
163660135e Create the new linker type "linker_private_weak_def_auto". 
It's similar to "linker_private_weak", but it's known that the address of the
object is not taken. For instance, functions that had an inline definition, but
the compiler decided not to inline it. Note, unlike linker_private and
linker_private_weak, linker_private_weak_def_auto may have only default
visibility.  The symbols are removed by the linker from the final linked image
(executable or dynamic library).

llvm-svn: 111684
 2010-08-20 22:05:50 +00:00
Bob Wilson
0039bc228b Replace the arm.neon.vmovls and vmovlu intrinsics with vector sign-extend and 
zero-extend operations.

llvm-svn: 111614
 2010-08-20 04:54:02 +00:00
Eric Christopher
e082792357 Fix loop conditionals (MO.isDef() asserts that it's a reg) and 
move some constraints around.

llvm-svn: 111594
 2010-08-20 00:36:24 +00:00
Eric Christopher
df3a3f5e3e Add a couple of random comments. 
llvm-svn: 111592
 2010-08-20 00:20:31 +00:00
Jim Grosbach
4e6f40561f Better handling of offsets on frame index references. rdar://8277890 
llvm-svn: 111585
 2010-08-19 23:52:25 +00:00
Jim Grosbach
d009b9d0a8 Add Thumb1 support for virtual frame indices. 
rdar://8277890

llvm-svn: 111533
 2010-08-19 17:52:13 +00:00
Eric Christopher
8f9362166c Silence warning. 
llvm-svn: 111518
 2010-08-19 15:35:27 +00:00
Chris Lattner
355d472093 fix PR7465, mishandling of lcall and ljmp: intersegment long 
call and jumps.

llvm-svn: 111496
 2010-08-19 01:18:43 +00:00
Chris Lattner
b3abfa861f minor progress towards fixing PR7465 
llvm-svn: 111494
 2010-08-19 01:00:34 +00:00
Eric Christopher
b80df4f04e Add an AddOptionalDefs method and use it. 
llvm-svn: 111489
 2010-08-19 00:37:05 +00:00
Bill Wendling
fa85185486 Add the "isCompare" attribute to the defm instead of each individual instr. 
llvm-svn: 111481
 2010-08-19 00:05:48 +00:00
Jakob Stoklund Olesen
f2b0bcb397 Don't call Predicate_* in Mips. 
llvm-svn: 111468
 2010-08-18 23:56:46 +00:00
Eric Christopher
0749ca13a8 Remove extra header. 
llvm-svn: 111456
 2010-08-18 23:38:16 +00:00
Jim Grosbach
6f036da8dc Enable ARM base register reuse to local stack slot allocation. Whenever a new 
frame index reference to an object in the local block is seen, check if
it's near enough to any previously allocaated base register to re-use.

rdar://8277890

llvm-svn: 111443
 2010-08-18 22:44:49 +00:00
Bill Wendling
d4fd98ebda Minor simplification. Gets rid of a needless temporary. 
llvm-svn: 111430
 2010-08-18 21:32:07 +00:00
Bill Wendling
fa83b9853e Marked with ATTRIBUTE_USED so that clang doesn't complain. 
llvm-svn: 111383
 2010-08-18 18:40:57 +00:00
Jim Grosbach
b517fe948f Add hook for re-using virtual base registers for local stack slot access. 
Nothing fancy, just ask the target if any currently available base reg
is in range for the instruction under consideration and use the first one
that is. Placeholder ARM implementation simply returns false for now.

ongoing saga of rdar://8277890

llvm-svn: 111374
 2010-08-18 17:57:37 +00:00
Kalle Raiskila
05d3cc2ef8 Fix a bug with insertelement on SPU. 
The previous algorithm in LowerVECTOR_SHUFFLE 
didn't check all requirements for "monotonic" shuffles.

llvm-svn: 111361
 2010-08-18 10:20:29 +00:00
Kalle Raiskila
8b6f5df4ae Remove all traces of v2[i,f]32 on SPU. 
The "half vectors" are now widened to full size by the legalizer.
The only exception is in parameter passing, where half vectors are 
expanded. This causes changes to some dejagnu tests.

llvm-svn: 111360
 2010-08-18 10:04:39 +00:00
Kalle Raiskila
0ee13a45c8 Change SPU C calling convention to match that described in 
"SPU Application Binary Interface Specification, v1.9" by
IBM. 
Specifically: use r3-r74 to pass parameters and the return value.

llvm-svn: 111358
 2010-08-18 09:50:30 +00:00