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5 Commits

Author SHA1 Message Date
Dmitry Preobrazhensky
4c3058cdb8 [AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_fork 
See https://bugs.llvm.org/show_bug.cgi?id=41888

Reviewers: artem.tamazov, arsenm

Differential Revision: https://reviews.llvm.org/D62016

llvm-svn: 361040
 2019-05-17 14:57:04 +00:00
Artem Tamazov
0b6855273a [AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers. 
Possibility to specify code of hardware register kept.
Disassemble to symbolic name, if name is known.
Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19335

llvm-svn: 267724
 2016-04-27 15:17:03 +00:00
Artem Tamazov
7fa01faba1 [AMDGPU][llvm-mc] s_getreg/setreg* - Add hwreg(...) syntax. 
Added hwreg(reg[,offset,width]) syntax.
Default offset = 0, default width = 32.
Possibility to specify 16-bit immediate kept.
Added out-of-range checks.
Disassembling is always to hwreg(...) format.
Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19329

llvm-svn: 267410
 2016-04-25 14:13:51 +00:00
Artem Tamazov
cc6f4e6962 [AMDGPU][llvm-mc] s_setreg* - Fix order of operands 
Order should match the sp3 syntax, where destination (simm16 denoting the hwreg) is coming first.

Differential Revision: http://reviews.llvm.org/D19161

llvm-svn: 266617
 2016-04-18 14:54:26 +00:00
Valery Pykhtin
a15ed0e818 [AMDGPU] add VI disassembler tests. NFC. 
Autogenerated from the corresponding assembler tests with a few FIXME added (will fix soon).

Differential Revision: http://reviews.llvm.org/D18249

llvm-svn: 263729
 2016-03-17 17:56:33 +00:00