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14 Commits

Author SHA1 Message Date
Craig Topper
bdb054a757 [X86] Make %eiz usage in 64-bit mode, force a 0x67 address size prefix. Fix some test CHECK lines. 
llvm-svn: 335414
 2018-06-23 06:15:04 +00:00
Craig Topper
8df61fd902 [X86] Stop printing moves between VR64 and GR64 with 'movd' mnemonic. Use 'movq' instead. 
This behavior existed to work with an old version of the gnu assembler on MacOS that only accepted this form. Newer versions of GNU assembler and the current LLVM derived version of the assembler on MacOS support movq as well.

llvm-svn: 321898
 2018-01-05 20:55:12 +00:00
Konstantin Belochapka
96e1c71c44 [X86] [MC] fixed non optimal encoding of instruction memory operand (PR24038). 
Fixed suboptimal encoding of instruction memory operand when assembler is used to select 32 bit fixup rather than 8 bit immediate for encoding memory offset value.
Differential Revision: https://reviews.llvm.org/D38117

llvm-svn: 314044
 2017-09-22 23:37:48 +00:00
Craig Topper
7124eab7a6 [X86] Fix printing of sha256rnds2 to include the implicit %xmm0 argument. 
llvm-svn: 294132
 2017-02-05 18:33:31 +00:00
Craig Topper
5a9b4168e7 [X86] Make fxsave64/fxrstor64/xsave64/xsrstor64/xsaveopt64 parseable in AT&T syntax. Also make them the default output. 
llvm-svn: 227963
 2015-02-03 11:03:57 +00:00
Craig Topper
1548551887 Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 
llvm-svn: 192567
 2013-10-14 04:55:01 +00:00
Craig Topper
c9050b2d46 Mark MOVMSKPS/MOVMSKPD/VPINSRWrr64i as AsmParserOnly to remove them from the disassembler tables. Add PINSRWrr64i to complement the AVX version. 
llvm-svn: 192565
 2013-10-14 01:21:22 +00:00
Craig Topper
60ef08db39 Allow non-AVX form of pmovmskb to take a GR64 operand. 
llvm-svn: 192341
 2013-10-10 05:33:31 +00:00
Ben Langmuir
1023593e49 Add the remaining Intel SHA instructions 
Also assembly/disassembly tests, and for sha256rnds2, aliases with an explicit
xmm0 dependency.

llvm-svn: 190754
 2013-09-14 15:03:21 +00:00
Ben Langmuir
9981cd7cfe Partial support for Intel SHA Extensions (sha1rnds4) 
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.

Support for the remaining instructions will follow in a separate patch.

llvm-svn: 190611
 2013-09-12 15:51:31 +00:00
Joerg Sonnenberger
42c3063de0 Add encoding tests for flds/filds 
llvm-svn: 129589
 2011-04-15 19:25:31 +00:00
Joerg Sonnenberger
9f8f3a2c59 Recognize leavel and leaveq aliases for leave. 
Validate encoding of leave in 64bit mode.

llvm-svn: 125795
 2011-02-17 23:36:39 +00:00
Reid Kleckner
0e68b2ed88 Add encodings and mnemonics for FXSAVE64 and FXRSTOR64. 
These are just FXSAVE and FXRSTOR with REX.W prefixes.  These versions use
64-bit pointer values instead of 32-bit pointer values in the memory map they
dump and restore.

llvm-svn: 125446
 2011-02-12 23:24:13 +00:00
Chris Lattner
2c53557b0d move X86 subdir up a level 
llvm-svn: 115292
 2010-10-01 04:32:20 +00:00