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Author SHA1 Message Date
Jim Grosbach
de78ccb013 Move the ARM so_imm encoding into a custom operand encoder and remove the 
explicit handling of the instructions referencing it from the MC code
emitter.

llvm-svn: 116367
 2010-10-12 23:18:08 +00:00
Jim Grosbach
0038f2eec6 Be nitpicky and line up the comments. 
llvm-svn: 116365
 2010-10-12 23:14:03 +00:00
Bill Wendling
d1f06024ce Refactor some of the encoding logic into a base class. This keeps us from having 
to add 10+ lines to every instruction.

It may turn out that we can move this base class into it's parent class.

llvm-svn: 116362
 2010-10-12 23:06:54 +00:00
Jim Grosbach
f4cf5bef46 Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360
 2010-10-12 23:00:24 +00:00
Bill Wendling
cd3cb8da45 Add encoding for VSUB and VCMP. 
Fear not! I'm going to try a refactoring right now. :)

llvm-svn: 116359
 2010-10-12 22:55:35 +00:00
Bill Wendling
fad2800dbd Don't need to specify calling convention. Add 'readnone' to functions. 
llvm-svn: 116354
 2010-10-12 22:24:10 +00:00
Jim Grosbach
394bc160f9 Allow targets to optionally specify custom binary encoder functions for 
operand values. This is useful for operands which require additional trickery
to encode into the instruction. For example, the ARM shifted immediate and
shifted register operands.

llvm-svn: 116353
 2010-10-12 22:21:57 +00:00
Bill Wendling
33a26354c1 Encoding for VADDD. Plus a test for the VFP instructions. 
llvm-svn: 116348
 2010-10-12 22:08:41 +00:00
Bill Wendling
79d57782ad Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.

llvm-svn: 116347
 2010-10-12 22:03:19 +00:00
Eric Christopher
af5b22e150 Fix thinko in arm fast isel alloca rewrite. 
llvm-svn: 116339
 2010-10-12 21:23:43 +00:00
Jim Grosbach
58ee6f3972 Encoding for ARM-mode VADD.F32 instruction. 
llvm-svn: 116338
 2010-10-12 21:22:40 +00:00
Owen Anderson
63f757463c Begin adding static dependence information to passes, which will allow us to 
perform initialization without static constructors AND without explicit initialization
by the client.  For the moment, passes are required to initialize both their
(potential) dependencies and any passes they preserve.  I hope to be able to relax
the latter requirement in the future.

llvm-svn: 116334
 2010-10-12 19:48:12 +00:00
Eric Christopher
303692631e Combine these together - should probably have some text associated 
that says what why what we just asserted is wrong.

llvm-svn: 116333
 2010-10-12 19:44:17 +00:00
Michael J. Spencer
26bda5a647 KillTheDoctor: Fix VS2008 build. 
llvm-svn: 116330
 2010-10-12 19:27:44 +00:00
Nick Lewycky
a6815ae877 Mark variable 'NoImplicitFloatOps' used only in an assert as used. 
llvm-svn: 116323
 2010-10-12 18:18:03 +00:00
Jim Grosbach
d18b416075 Comment grammar tweakage. 
llvm-svn: 116322
 2010-10-12 18:11:41 +00:00
Jim Grosbach
a0f673b561 Add MOVi ARM encoding. 
llvm-svn: 116321
 2010-10-12 18:09:12 +00:00
Dan Gohman
d904add908 Initial va_arg support for x86-64. Patch by David Meyer! 
llvm-svn: 116319
 2010-10-12 18:00:49 +00:00
Jim Grosbach
dbf116be66 Nuke unused wrapper function. 
llvm-svn: 116318
 2010-10-12 17:53:25 +00:00
Jakob Stoklund Olesen
499fe39d23 Remove the x86 MOV{32,64}{rr,rm,mr}_TC instructions. 
The reg-reg copies were no longer being generated since copyPhysReg copies
physical registers only.

The loads and stores are not necessary - The TC constraint is imposed by the
TAILJMP and TCRETURN instructions, there should be no need for constrained loads
and stores.

llvm-svn: 116314
 2010-10-12 17:15:00 +00:00
Jim Grosbach
10d9bbe0ca Add encoding information for the remainder of the generic arithmetic 
ARM instructions.

llvm-svn: 116313
 2010-10-12 17:11:26 +00:00
Bob Wilson
bbb91c6a1c PR8359: The ARM backend may end up allocating registers D16 to D31 when 
"-mattr=+vfp3" is specified. However, this will not work for hardware that
only supports 16 registers.  Add a new flag to support -"mattr=+vfp3,+d16".
Patch by Jan Voung!

llvm-svn: 116310
 2010-10-12 16:22:47 +00:00
Eric Christopher
0763cc04c5 Rework alloca handling so that we can load or store from casted 
address that we've looked through.

Fixes compilation problems in tramp3d from earlier patch.

llvm-svn: 116296
 2010-10-12 05:39:06 +00:00
Eric Christopher
8a4621b7df Fix the last two commits to configure - configure is a generated file. 
Made necessary edits to configure.ac and regenerated.

llvm-svn: 116291
 2010-10-12 02:42:05 +00:00
Eric Christopher
8789aa8799 Handle a wider arrangement of loads. 
llvm-svn: 116284
 2010-10-12 00:43:21 +00:00
Cameron Esfahani
71cdbd5d44 Fix spelling error. 
llvm-svn: 116282
 2010-10-12 00:21:05 +00:00
Dan Gohman
d1789c3cef Delete a redundant check. 
llvm-svn: 116280
 2010-10-12 00:19:24 +00:00
Dan Gohman
3b55a1294e More SmallVectorImpls. 
llvm-svn: 116279
 2010-10-12 00:15:27 +00:00
Dan Gohman
cca2c82199 Shrink a SmallVector with a known maximum size. 
llvm-svn: 116278
 2010-10-12 00:13:43 +00:00
Dan Gohman
c49d367fb9 Constify. 
llvm-svn: 116277
 2010-10-12 00:12:29 +00:00
Dan Gohman
dbb5a62aba Use SmallVectorImpl in a bunch of places. 
llvm-svn: 116276
 2010-10-12 00:11:18 +00:00
Francois Pichet
6bf8a81c52 Disable warning C4267 for MSVC. Otherwise it generate literally thousands of warnings when targeting x64. The warning occurs because int is 32 bit but size_t is 64 bit on Win64. 
llvm-svn: 116274
 2010-10-12 00:01:36 +00:00
Dan Gohman
8dc9781a91 Add a simple testcase for tbaa. 
llvm-svn: 116272
 2010-10-11 23:54:13 +00:00
Evan Cheng
6aac1548ab More ARM scheduling itinerary fixes. 
llvm-svn: 116266
 2010-10-11 23:41:41 +00:00
Dan Gohman
4231230501 Support AA chaining. 
llvm-svn: 116264
 2010-10-11 23:39:34 +00:00
Dan Gohman
3d1fa9f524 Fix the pass manager's search order for immutable passes, and make it 
stop searching when it has found a match.

llvm-svn: 116262
 2010-10-11 23:19:01 +00:00
Jim Grosbach
29ef87e765 MC machine encoding for simple aritmetic instructions that use a shifted 
register operand.

llvm-svn: 116259
 2010-10-11 23:16:21 +00:00
Jason W Kim
59375bae75 Second set of ARM/MC/ELF changes. 
Added ARM specific ELF section types.
Added AttributesSection to ARMElfTargetObject
First step in unifying .cpu assembly tag with ELF/.o
llc now asserts on actual ELF emission on -filetype=obj :-)

llvm-svn: 116257
 2010-10-11 23:01:44 +00:00
Dan Gohman
68f316a93c Clang's #include handling apparently doesn't work for libstdc++'s 
fenv.h. See PR6907 for details. Work around this in FEnv.h to fix
the seflhost build.

llvm-svn: 116256
 2010-10-11 22:30:59 +00:00
Michael J. Spencer
6b47972a41 Unit Tests: Missed this error. MSVC and clang didn't complain. 
llvm-svn: 116252
 2010-10-11 22:04:38 +00:00
Evan Cheng
77ba7b098a Proper VST scheduling itineraries. 
llvm-svn: 116251
 2010-10-11 22:03:18 +00:00
Eric Christopher
e1574aa60a Use a sane mechanism for that assert. 
llvm-svn: 116249
 2010-10-11 22:01:22 +00:00
Michael J. Spencer
0888ccaa19 System: Add SwapByteOrder and update Support/MathExtras.h to use it. 
This time correctly.

llvm-svn: 116247
 2010-10-11 21:56:16 +00:00
Jakob Stoklund Olesen
44943ef3f8 Replace FindLiveRangeContaining() with getVNInfoAt() in LiveIntervalAnalysis. 
This helps hiding the LiveRange class which really should be private.

llvm-svn: 116244
 2010-10-11 21:45:03 +00:00
Jim Grosbach
06a0fb7aff The assert() should reference to machine instr operand number, too. 
llvm-svn: 116243
 2010-10-11 21:41:31 +00:00
Michael J. Spencer
0af3659b5d Revert "System: Add SwapByteOrder and update Support/MathExtras.h to use it." 
This reverts commit 116234.

It compiled just fine with MSVC and clang...

llvm-svn: 116242
 2010-10-11 21:39:24 +00:00
Eric Christopher
926a41a84b We're not going to handle dynamic allocas anywhere else. 
llvm-svn: 116240
 2010-10-11 21:37:35 +00:00
Daniel Dunbar
2b6bcb4978 Change explicit search Apple specific code to only reference __eprintf on x86. 
llvm-svn: 116239
 2010-10-11 21:34:24 +00:00
Jim Grosbach
bfc337878b Make sure to use the machine instruction operand number. It doesn't always 
map one-to-one with the CodeGenInstruction operand number.

llvm-svn: 116238
 2010-10-11 21:31:22 +00:00
Michael J. Spencer
29e2ba9ca8 Reduce dpendencies for SupportTests. 
llvm-svn: 116235
 2010-10-11 21:22:34 +00:00