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3482 Commits

Author SHA1 Message Date
Chris Lattner
8e0dfe133c Modify the TargetLowering::getPackedTypeBreakdown method to also return the 
unpromoted element type.

llvm-svn: 27273
 2006-03-31 00:46:36 +00:00
Chris Lattner
557951b354 Add a method useful for decimating vectors. 
llvm-svn: 27269
 2006-03-31 00:28:23 +00:00
Chris Lattner
e35e1db8c2 fix incorrect prototypes 
llvm-svn: 27267
 2006-03-30 23:32:58 +00:00
Chris Lattner
69148453d0 Add vector multiply, multiply sum, pack, unpack, and lvsl/lvsr intrinsics. 
llvm-svn: 27258
 2006-03-30 18:52:02 +00:00
Evan Cheng
57d481a78a Add support for _mm_cmp{cc}_ss and _mm_cmp{cc}_ps intrinsics 
llvm-svn: 27256
 2006-03-30 06:21:22 +00:00
Evan Cheng
82d2a6910f Add 128-bit pmovmskb intrinsic support. 
llvm-svn: 27255
 2006-03-30 00:33:26 +00:00
Evan Cheng
9ebe75e915 Change SSE pack operation definitions to fit what the intrinsics expected. 
For example, packsswb actually creates a v16i8 from a pair of v8i16. But since
the intrinsic specification forces the output type to match the operands.

llvm-svn: 27254
 2006-03-29 23:53:14 +00:00
Evan Cheng
1b19ed24d6 Add SSE2 integer pack with saturation intrinsics. 
llvm-svn: 27253
 2006-03-29 23:09:19 +00:00
Evan Cheng
84c8b5bcd9 Add more SSE intrinsics 
llvm-svn: 27247
 2006-03-29 06:07:16 +00:00
Chris Lattner
83ec289ebf Add a new node 
llvm-svn: 27230
 2006-03-28 19:54:11 +00:00
Jim Laskey
4c2d4d1912 Refactor address attributes. Add base register to frame info. 
llvm-svn: 27226
 2006-03-28 14:58:32 +00:00
Jim Laskey
eb38a3e83a Expose base register for DwarfWriter. Refactor code accordingly. 
llvm-svn: 27225
 2006-03-28 13:48:33 +00:00
Nate Begeman
5a82c8ccbd Add a few more altivec intrinsics 
llvm-svn: 27215
 2006-03-28 04:15:58 +00:00
Chris Lattner
1a5116bd0c These don't directly map to gcc intrinsics any more. 
llvm-svn: 27213
 2006-03-28 03:52:36 +00:00
Chris Lattner
176d16aec7 Add some more intrinsics: rotates, fp rounds, and random other fp instructions. 
llvm-svn: 27208
 2006-03-28 02:28:48 +00:00
Evan Cheng
d10153ba72 getVectorTyppe(MVT::i64, 2) ==> MVT::v2i64. 
llvm-svn: 27207
 2006-03-28 01:59:17 +00:00
Chris Lattner
76ce849af5 Add lvxl 
llvm-svn: 27206
 2006-03-28 01:49:27 +00:00
Chris Lattner
a0f80c3c3f Tblgen doesn't like multiple SDNode<> definitions that map to the same 
enum value.  Split them into separate enums.

llvm-svn: 27199
 2006-03-28 00:39:06 +00:00
Chris Lattner
b53e0ddbd3 Reenable pointer intrinsics. 
llvm-svn: 27198
 2006-03-28 00:15:44 +00:00
Chris Lattner
1e517cbb0c revert this, it breaks things 
llvm-svn: 27195
 2006-03-28 00:02:52 +00:00
Jim Laskey
1585be504a Should not remove casts from variable's alloca. 
llvm-svn: 27191
 2006-03-27 23:30:18 +00:00
Chris Lattner
720a11dd3e Add support for intrinsics with pointer arguments in target .td files. 
llvm-svn: 27190
 2006-03-27 22:49:46 +00:00
Chris Lattner
a6ae3e278a Add some missing template specializations for autodereferencing User. 
llvm-svn: 27189
 2006-03-27 22:49:07 +00:00
Chris Lattner
fd3aa5f890 add a new iPTR ValueType for tblgen use 
llvm-svn: 27187
 2006-03-27 22:48:00 +00:00
Chris Lattner
6917dae72b Divirge from the GCC specification of the load/store intrinsics: only take 
one pointer operand, instead of a pointer and an offset.  The FE will lower
to this canonicalized form.

llvm-svn: 27186
 2006-03-27 22:38:39 +00:00
Chris Lattner
735fa11e56 fix spelling :( 
llvm-svn: 27184
 2006-03-27 22:07:12 +00:00
Chris Lattner
37cd00ed2a add some more intrinsics. 
llvm-svn: 27183
 2006-03-27 22:05:34 +00:00
Evan Cheng
aba79c636f Intrinsics naming convention change. 
llvm-svn: 27172
 2006-03-27 08:23:12 +00:00
Evan Cheng
4667bd17cb Change isBuildVectorAllOnesInteger to isBuildVectorAllOnes. Also check for 
floating point cases.

llvm-svn: 27165
 2006-03-27 06:58:47 +00:00
Nate Begeman
3d518334b9 SelectionDAGISel can now natively handle Switch instructions, in the same 
manner that the LowerSwitch LLVM to LLVM pass does: emitting a binary
search tree of basic blocks.  The new approach has several advantages:
it is faster, it generates significantly smaller code in many cases, and
it paves the way for implementing dense switch tables as a jump table by
handling switches directly in the instruction selector.

This functionality is currently only enabled on x86, but should be safe for
every target.  In anticipation of making it the default, the cfg is now
properly updated in the x86, ppc, and sparc select lowering code.

llvm-svn: 27156
 2006-03-27 01:32:24 +00:00
Jim Laskey
278ca1e735 How to be dumb on $5/day. Need a tri-state to track valid debug descriptors. 
llvm-svn: 27154
 2006-03-26 22:45:20 +00:00
Evan Cheng
ef3b33b847 Add ISD::isBuildVectorAllZeros predicate 
llvm-svn: 27147
 2006-03-26 09:50:58 +00:00
Chris Lattner
0069646b1d Add predicate comparison intrinsics. 
llvm-svn: 27145
 2006-03-26 07:50:25 +00:00
Chris Lattner
d8f528f04f Split the PPC and X86 intrinsics out to their own files. 
llvm-svn: 27141
 2006-03-26 02:37:19 +00:00
Chris Lattner
83cad7bff6 Add saturating subtracts, non-predicate compares, and some other random 
intrinsics.

llvm-svn: 27140
 2006-03-26 02:34:07 +00:00
Chris Lattner
9ecf506a2f add int_ppc_altivec_vsldoi intrinsic 
llvm-svn: 27138
 2006-03-26 00:25:43 +00:00
Chris Lattner
91fe1d4b55 Add a predicate 
llvm-svn: 27129
 2006-03-25 22:56:35 +00:00
Jim Laskey
576323f04f Unused function - easier to throw away than fix. 
llvm-svn: 27123
 2006-03-25 18:42:45 +00:00
Chris Lattner
06a3ec70c9 remove extraneous lets 
llvm-svn: 27114
 2006-03-25 07:30:34 +00:00
Chris Lattner
e767292e67 Add a bunch of simple altivec intrinsics 
llvm-svn: 27113
 2006-03-25 07:27:18 +00:00
Chris Lattner
33f07e82dc Add support for __builtin_altivec_vnmsubfp 
llvm-svn: 27111
 2006-03-25 07:05:35 +00:00
Chris Lattner
2ed67c5d0f Add a programatic interface to intrinsic names. 
llvm-svn: 27107
 2006-03-25 06:32:07 +00:00
Evan Cheng
ff65ba0857 X86 SSE1 cacheability support ops intrinsics 
llvm-svn: 27104
 2006-03-25 06:05:45 +00:00
Evan Cheng
ad4f96ae46 X86 SSE1 SIMD store intrinsics. 
llvm-svn: 27099
 2006-03-25 02:02:51 +00:00
Evan Cheng
35a181d293 X86 SSE1 SIMD load intrinsics (movhps, movlps, and movups). 
llvm-svn: 27098
 2006-03-25 01:58:54 +00:00
Evan Cheng
b58801303a X86 SSE1 conversion operations intrinsics. 
llvm-svn: 27097
 2006-03-25 01:35:17 +00:00
Evan Cheng
35bbc93d35 X86 SSE1 comparison intrinsics. 
llvm-svn: 27093
 2006-03-25 00:32:32 +00:00
Evan Cheng
e3f4eecb44 X86 SSE1 arithmetic and logical operation intrinsics. 
llvm-svn: 27092
 2006-03-25 00:18:20 +00:00
Evan Cheng
83c1f2e316 ldmxcsr is a SSE instruction. 
llvm-svn: 27086
 2006-03-24 22:13:47 +00:00
Evan Cheng
b98a5e8507 Added ldmxcsr intrinsic. 
llvm-svn: 27085
 2006-03-24 22:10:59 +00:00