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Commit Graph

167437 Commits

Author SHA1 Message Date
Eli Friedman
5e3a3e7469 [GlobalMerge] Allow merging globals with explicit section markings.
At least on ELF, it's impossible to tell from the object file whether
two globals with the same section marking were merged: the merged global
uses "private" linkage to hide its symbol, and the aliases look like
regular symbols. I can't think of any other reason to disallow it.
(Of course, we can only merge globals in the same section.)

The weird alignment handling matches AsmPrinter; our alignment handling
for global variables should probably be refactored.

Differential Revision: https://reviews.llvm.org/D49822

llvm-svn: 338791
2018-08-02 23:54:16 +00:00
Tim Renouf
c1efbeb4fd [AMDGPU] Minor change to d16 buffer load implementation
Summary:
By not reconstructing the operand list of the SDNode, this change makes
it easier to add the forthcoming new tbuffer and buffer intrinsics.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D49995

Change-Id: I0cb79ef0801532645d7dd954a6d7355139db7b38
llvm-svn: 338784
2018-08-02 23:33:01 +00:00
Tim Renouf
991d99708a [AMDGPU] Reworked SIFixWWMLiveness
Summary:
I encountered some problems with SIFixWWMLiveness when WWM is in a loop:

1. It sometimes gave invalid MIR where there is some control flow path
   to the new implicit use of a register on EXIT_WWM that does not pass
   through any def.

2. There were lots of false positives of registers that needed to have
   an implicit use added to EXIT_WWM.

3. Adding an implicit use to EXIT_WWM (and adding an implicit def just
   before the WWM code, which I tried in order to fix (1)) caused lots
   of the values to be spilled and reloaded unnecessarily.

This commit is a rework of SIFixWWMLiveness, with the following changes:

1. Instead of considering any register with a def that can reach the WWM
   code and a def that can be reached from the WWM code, it now
   considers three specific cases that need to be handled.

2. A register that needs liveness over WWM to be synthesized now has it
   done by adding itself as an implicit use to defs other than the
   dominant one.

Also added the following fixmes:

FIXME: We should detect whether a register in one of the above
categories is already live at the WWM code before deciding to add the
implicit uses to synthesize its liveness.

FIXME: I believe this whole scheme may be flawed due to the possibility
of the register allocator doing live interval splitting.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D46756

Change-Id: Ie7fba0ede0378849181df3f1a9a7a39ed1a94a94
llvm-svn: 338783
2018-08-02 23:31:32 +00:00
Craig Topper
27e7f59c1b [X86] Allow 'atomic_store (neg/not atomic_load)' to isel to a RMW instruction.
There was a FIXMe in the td file about a type inference issue that was easy to fix.

llvm-svn: 338782
2018-08-02 23:30:38 +00:00
Craig Topper
e101b55688 [X86] Add NEG and NOT test cases to atomic_mi.ll in preparation for fixing the FIXME in X86InstrCompiler.td to make these work for atomic load/store.
llvm-svn: 338781
2018-08-02 23:30:31 +00:00
Tim Renouf
faff37a910 [AMDGPU] Avoid using divergent value in mubuf addr64 descriptor
Summary:
This fixes a problem where a load from global+idx generated incorrect
code on <=gfx7 when the index is divergent.

Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D47383

Change-Id: Ib4d177d6254b1dd3f8ec0203fdddec94bd8bc5ed
llvm-svn: 338779
2018-08-02 22:53:57 +00:00
Zachary Turner
770b562212 [MS Demangler] Fix some tests that are no longer broken.
These were fixed with earlier patches, but had not yet been
re-enabled.

llvm-svn: 338778
2018-08-02 22:37:40 +00:00
Krzysztof Parzyszek
db3c93e416 [Hexagon] Simplify CFG after atomic expansion
This will remove suboptimal branching from the generated ll/sc loops.
The extra simplification pass affects a lot of testcases, which have
been modified to accommodate this change: either by modifying the
test to become immune to the CFG simplification, or (less preferablt)
by adding option -hexagon-initial-cfg-clenaup=0.

llvm-svn: 338774
2018-08-02 22:17:53 +00:00
Heejin Ahn
855cdeda11 [WebAssembly] Support for atomic.wait / atomic.wake instructions
Summary:
This adds support for atomic.wait / atomic.wake instructions in the wasm
thread proposal.

Reviewers: dschuff

Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits

Differential Revision: https://reviews.llvm.org/D49395

llvm-svn: 338770
2018-08-02 21:44:24 +00:00
Krzysztof Parzyszek
67370a2e75 [Unittests] Fix returning string in SolveQuadraticEquationWrap
Returning a Twine caused runtime failures. Convert it to std::string
before retuning.

llvm-svn: 338768
2018-08-02 20:45:06 +00:00
Craig Topper
48854aaf43 [X86] Autogenerate complete checks. NFC
llvm-svn: 338765
2018-08-02 20:28:45 +00:00
Lang Hames
54d28c92f1 [ORC] Add a re-exports fallback definition generator.
An instance of ReexportsFallbackDefinitionGenerator can be attached to a VSO
(via setFallbackDefinitionGenerator) to re-export symbols on demandy from a
backing VSO.

llvm-svn: 338764
2018-08-02 20:13:58 +00:00
George Burgess IV
d33befca30 [Support] Add an enable bit to our DebugCounters
r337748 made us start incrementing DebugCounters all of the time. This
makes tsan unhappy in multithreaded environments.

Since it doesn't make much sense to use DebugCounters with multiple
threads, this patch makes us only count anything if the user passed a
-debug-counter option or if some other piece of code explicitly asks
for it (e.g. the pass in D50031).

The amount of global state here makes writing a unittest for this
behavior somewhat awkward. So, no test is provided.

Differential Revision: https://reviews.llvm.org/D50150

llvm-svn: 338762
2018-08-02 19:50:27 +00:00
Krzysztof Parzyszek
825db0d74d Unbreak build after r338758: specify lambda return type explicitly
llvm-svn: 338760
2018-08-02 19:38:18 +00:00
Paul Robinson
17be6b162b [DebugInfo/DWARF] Remove redundant iterator type. NFC
llvm-svn: 338759
2018-08-02 19:29:38 +00:00
Krzysztof Parzyszek
e5e129cd68 [SCEV] Properly solve quadratic equations
Differential Revision: https://reviews.llvm.org/D48283

llvm-svn: 338758
2018-08-02 19:13:35 +00:00
Bob Haarman
042dbe8263 [Support] [NFC] change comment about retries in createUniqueEntity
Rewording as requested on D50126 after the change was pushed.

llvm-svn: 338755
2018-08-02 18:27:21 +00:00
Puyan Lotfi
1a21a7dd5b [NFC] clang-format cleanup of a couple files in llvm-objcopy.
llvm-svn: 338752
2018-08-02 18:16:52 +00:00
Tom Stellard
04af371897 CMake: Remove LLVM_DYLIB_SYMBOL_VERSIONING
Summary:
This option is no longer needed since r300496 added symbol
versioning by default

Reviewers: sylvestre.ledru, beanz, mgorny

Reviewed By: mgorny

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D49835

llvm-svn: 338751
2018-08-02 18:16:10 +00:00
Erik Pilkington
d885a2d9d5 [itanium demangler] Support dot suffixes on block invocation functions
rdar://32378759

llvm-svn: 338747
2018-08-02 17:45:01 +00:00
Bob Haarman
9a06bfd66a [Support] fix TempFile infinite loop and permission denied errors
Summary:
On Windows, TempFile::create() was prone to failing with permission
denied errors when a process created many tempfiles without providing
a model large enough to accommodate them. There was also a problem
with createUniqueEntity getting into an infinite loop when all names
permitted by the model are in use. This change fixes both of these
problems and adds a unit test for them.

Reviewers: pcc, rnk, zturner

Reviewed By: zturner

Subscribers: inglorion, hiraditya, llvm-commits

Differential Revision: https://reviews.llvm.org/D50126

llvm-svn: 338745
2018-08-02 17:41:38 +00:00
Sam Clegg
176975c51f [WebAssembly] Ensure bitcasts that would result in invalid wasm are removed by FixFunctionBitcasts
Rather than allowing invalid bitcasts to be lowered to wasm
call instructions that won't validate, generate wrappers that
contain unreachable thereby delaying the error until runtime.

Differential Revision: https://reviews.llvm.org/D49517

llvm-svn: 338744
2018-08-02 17:38:06 +00:00
Zachary Turner
474432490e Fix one more warning.
llvm-svn: 338742
2018-08-02 17:33:33 +00:00
Zachary Turner
9560bf0466 Update the LLVM VS integration to sign the assembly.
llvm-svn: 338740
2018-08-02 17:20:31 +00:00
Zachary Turner
1fe2393239 Fix a couple of warnings.
llvm-svn: 338739
2018-08-02 17:18:01 +00:00
Zachary Turner
5f1a862f35 Use %.*s instead of %*s when formatting strings with explicit length.
llvm-svn: 338737
2018-08-02 17:08:24 +00:00
Zachary Turner
a1fabd04e3 [MS Demangler] Resolve back-references lazily.
We need to both record and resolve back-references lazily due to
not being able to know until a demangling is complete whether or
not a name should go into the back-reference table..  This patch
implements lazy resolution of back-references, but we still have
eager recording of back-references.  This will be fixed in a
subsequent patch.

llvm-svn: 338736
2018-08-02 17:08:03 +00:00
Craig Topper
be5af31f5c [X86] Allow fake unary unpckhpd and movhlps to be commuted for execution domain fixing purposes
These instructions perform the same operation, but the semantic of which operand is destroyed is reversed. If the same register is used as both operands we can change the execution domain without worrying about this difference.

Unfortunately, this really only works in cases where the input register is killed by the instruction. If its not killed, the two address isntruction pass inserts a copy that will become a move instruction. This makes the instruction use different physical registers that contain the same data at the time the unpck/movhlps executes. I've considered using a unary pseudo instruction with tied operand to trick the two address instruction pass. We could then expand the pseudo post regalloc to get the same physical register on both inputs.

Differential Revision: https://reviews.llvm.org/D50157

llvm-svn: 338735
2018-08-02 16:48:01 +00:00
Evandro Menezes
35ae7d037c [SLC] Refactor simplification of pow() (NFC)
llvm-svn: 338730
2018-08-02 15:43:57 +00:00
Simon Pilgrim
0ddccae066 [X86][SSE] Add uniform/non-uniform exact sdiv vector tests covering all paths
Regenerated tests and tested on 64-bit (AVX2) as well.

llvm-svn: 338729
2018-08-02 15:34:51 +00:00
David Bolvansky
1b470bea6c [InstCombine] [NFC] Tests for select with binop fold
llvm-svn: 338727
2018-08-02 14:59:23 +00:00
Sanjay Patel
ac7ce106a1 [InstSimplify] move minnum/maxnum with undef fold from instcombine
llvm-svn: 338719
2018-08-02 14:33:40 +00:00
Sjoerd Meijer
082b54e3ed [ARM][NFC] Follow up of r338568
I disabled more tests than necessary, this enables them.

llvm-svn: 338717
2018-08-02 14:04:48 +00:00
Sanjay Patel
988613b6b6 [ValueTracking] fix maxnum miscompile for cannotBeOrderedLessThanZero (PR37776)
This adds the NAN checks suggested in PR37776:
https://bugs.llvm.org/show_bug.cgi?id=37776

If both operands to maxnum are NAN, that should get constant folded, so we don't 
have to handle that case. This is the same assumption as other FP ops in this
function. Returning 'false' is always conservatively correct.

Copying from the bug report:

Currently, we have this for "when is cannotBeOrderedLessThanZero 
(mustBePositiveOrNaN) true for maxnum":
               L
        -------------------
        | Pos | Neg | NaN |
   ------------------------
   |Pos |  x  |  x  |  x  |
   ------------------------
 R |Neg |  x  |     |  x  |
   ------------------------
   |NaN |  x  |  x  |  x  |
   ------------------------


The cases with (Neg & NaN) are wrong. We should have:

                L
        -------------------
        | Pos | Neg | NaN |
   ------------------------
   |Pos |  x  |  x  |  x  |
   ------------------------
 R |Neg |  x  |     |     |
   ------------------------
   |NaN |  x  |     |  x  |
   ------------------------

Differential Revision: https://reviews.llvm.org/D50081

llvm-svn: 338716
2018-08-02 13:46:20 +00:00
Matt Arsenault
6d0accb5a3 DAG: Fix vector widening fcanonicalize
llvm-svn: 338715
2018-08-02 13:43:53 +00:00
Matt Arsenault
5e71c6a155 AMDGPU: Fix scalarizing v4f16 fcanonicalize
llvm-svn: 338714
2018-08-02 13:43:42 +00:00
Ben Dunbobbin
46d88ebd0c [llvm-ar] Fix help text test. NFC.
Missed from @338703

llvm-svn: 338709
2018-08-02 12:27:01 +00:00
Ben Dunbobbin
ede5cc86c7 [llvm-ar] Correct help text
Corrected and simplified the help text.

It was clearly too difficult to maintain before (see e.g. @227296) making it
simpler and more consistent it should help people keep it up to date.

Differential Revision: https://reviews.llvm.org/D48577

llvm-svn: 338703
2018-08-02 11:27:38 +00:00
Andrea Di Biagio
8b13141f92 [llvm-mca] Use a vector to store ResourceState objects in the ResourceManager.
We don't need to use a map to store ResourceState objects. The number of
processor resources is known statically from the scheduling model. We can
therefore use a vector, and reserve a slot for each processor resource that we
want to simulate.
Every time the ResourceManager queries the ResourceState vector, the index to
the vector of ResourceState objects can be easily computed from the processor
resource mask.

This drastically reduces the time complexity of method ResourceManager::use() and
method ResourceManager::release(). This patch gives an average speedup of 12%.

llvm-svn: 338702
2018-08-02 11:12:35 +00:00
Guillaume Chatelet
4c5dcde9ea [llvm-exegesis] Rename InstructionInstance into InstructionBuilder.
Summary: Non functional change.

Subscribers: tschuett, courbet, llvm-commits

Differential Revision: https://reviews.llvm.org/D50176

llvm-svn: 338701
2018-08-02 11:12:02 +00:00
Simon Pilgrim
c88068b889 [X86][SSE] Add more UDIV nonuniform-constant vector tests
Ensure we cover all paths for vector data as requested on D49248

llvm-svn: 338698
2018-08-02 10:53:53 +00:00
Stefan Granitz
f43b171255 Add include guard
Summary: Add missing include guard LLVM_DEMANGLE_DEMANGLE_H in llvm/Demangle/Demangle.h

Reviewers: erik.pilkington

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D50042

llvm-svn: 338694
2018-08-02 09:45:59 +00:00
Simon Pilgrim
c8932c8635 [X86][SSE] Pull out duplicate VSELECT to shuffle mask code. NFCI.
llvm-svn: 338693
2018-08-02 09:20:27 +00:00
Alexander Ivchenko
ea50603b8f [GlobalISel] Fix typo with missed override specifier
llvm-svn: 338689
2018-08-02 08:55:05 +00:00
Andrew Savonichev
c0f1a2b3f6 [emacs] Indent statement continuation to match clang-format
Summary:
Was:

  int LongVariableName =
    veryLongFunctionNameThatExceeds80ColumnsRule(SomeParameter);

  int ShortVar = veryLongFunctionNameThatStillFitsIntoOneLine(SomeParameter)
    .nowThisDoesntFit()
    .andThis()

Now:

  int LongVariableName =
      veryLongFunctionNameThatExceeds80ColumnsRule(SomeParameter);

  int ShortVar = veryLongFunctionNameThatStillFitsIntoOneLine(SomeParameter)
                     .nowThisDoesntFit()
                     .andThis()


Reviewers: espindola, MaskRay

Reviewed By: MaskRay

Subscribers: greened, llvm-commits

Differential Revision: https://reviews.llvm.org/D49726

llvm-svn: 338686
2018-08-02 08:50:41 +00:00
Alexander Ivchenko
67b31b9526 [GlobalISel] Rewrite CallLowering::lowerReturn to accept multiple VRegs per Value
This is logical continuation of https://reviews.llvm.org/D46018 (r332449)

Differential Revision: https://reviews.llvm.org/D49660

llvm-svn: 338685
2018-08-02 08:33:31 +00:00
Hans Wennborg
5e7bf22541 utils/release/tag.sh: add debuginfo-tests to project list
llvm-svn: 338682
2018-08-02 08:10:34 +00:00
Hans Wennborg
1e673b607d lit: bump version number
llvm-svn: 338677
2018-08-02 07:48:44 +00:00
David Green
8365fa4252 [UnJ] Add debug messages for why loops are not unrolled. NFC
Adds some cleaned up debug messages from back when I was writing this.
Hopefully useful to others (and myself) as to why unroll and jam is not
transforming as expected.

Differential Revision: https://reviews.llvm.org/D50062

llvm-svn: 338676
2018-08-02 07:30:53 +00:00
David Green
7170871c24 [AArch64] Add support for got relocated LDR's
As a part of adding the tiny codemodel, we need to support ldr's with :got:
relocations on them. This seems to be mostly already done, just needs the
relocation type support.

Differential Revision: https://reviews.llvm.org/D50137

llvm-svn: 338673
2018-08-02 06:24:40 +00:00