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49 Commits

Author SHA1 Message Date
Duraid Madina
02b497f15a fix storing bools to mem and unordered FP ops 
llvm-svn: 31920
 2006-11-26 04:34:26 +00:00
Evan Cheng
92eb9a1639 Remove a duplicate pattern. 
llvm-svn: 29414
 2006-07-31 18:43:10 +00:00
Duraid Madina
a3c5cd22e1 doo de doo 
llvm-svn: 26614
 2006-03-08 06:18:46 +00:00
Duraid Madina
a514d8d8a6 now short immediates will get matched (previously constants were all 
triggering movl 64bit imm fat instructions)

llvm-svn: 26119
 2006-02-11 07:32:15 +00:00
Chris Lattner
20d4194a0d PHI and INLINEASM are now built-in instructions provided by Target.td 
llvm-svn: 25674
 2006-01-27 01:46:15 +00:00
Duraid Madina
13335846a8 some hoovering 
llvm-svn: 25643
 2006-01-26 09:08:31 +00:00
Duraid Madina
7d51a9b8e3 add bundling! well not really, for now it's just stop-insertion. 
llvm-svn: 25593
 2006-01-25 02:23:38 +00:00
Duraid Madina
2715941e86 remove RET hack, add proper support for rets (watching out for ret voids) 
llvm-svn: 25486
 2006-01-20 20:24:31 +00:00
Duraid Madina
b18a42fd3a fix storing bools! eek! 
llvm-svn: 25476
 2006-01-20 03:40:25 +00:00
Duraid Madina
069b517767 fix boolean XOR (which fixes up comparisons..) 
llvm-svn: 25462
 2006-01-19 15:18:56 +00:00
Duraid Madina
365cb4f82d use proper (82-bit) spills/fills when spilling FP regs, so that 
divides don't get broken. this fixes obsequi, smg2000, and probably
a bunch of other stuff (tm)

llvm-svn: 25385
 2006-01-17 02:04:52 +00:00
Duraid Madina
12da32f440 fix division! again!! pattern isel, prepare to die. 
llvm-svn: 25353
 2006-01-16 06:33:38 +00:00
Duraid Madina
3246f5317b this just might work 
llvm-svn: 25195
 2006-01-11 01:38:07 +00:00
Duraid Madina
242414e621 add support for selecting bools 
FIXME: this is commented out because it makes tblgen go a bit fruity
llvm-svn: 25193
 2006-01-11 01:21:12 +00:00
Evan Cheng
231b11ba87 Added field noResults to Instruction. 
Currently tblgen cannot tell which operands in the operand list are results so
it assumes the first one is a result. This is bad. Ideally we would fix this
by separating results from inputs, e.g. (res R32:$dst),
(ops R32:$src1, R32:$src2). But that's a more distruptive change. Adding
'let noResults = 1' is the workaround to tell tblgen that the instruction does
not produces a result. It works for now since tblgen does not support
instructions which produce multiple results.

llvm-svn: 25017
 2005-12-26 09:11:45 +00:00
Duraid Madina
00fbe7a7e4 we don't feed our call instructions extra operands 
llvm-svn: 25009
 2005-12-25 14:07:01 +00:00
Duraid Madina
bf2a5de0d5 oops, back this out 
llvm-svn: 24950
 2005-12-22 07:13:51 +00:00
Duraid Madina
d1c9d5ae4d we need to emit the getf.d instruction in lowering, so add it 
to IA64ISD

llvm-svn: 24946
 2005-12-22 06:38:38 +00:00
Duraid Madina
2c940da498 update tablegen files - nothing to see here 
llvm-svn: 24939
 2005-12-22 03:56:03 +00:00
Chris Lattner
487742bf85 Add some explicit type casts so that tblgen knows the type of the shiftamount, which is not necessarily the same as the type being shifted. 
llvm-svn: 24595
 2005-12-05 02:34:29 +00:00
Duraid Madina
a60348b6b2 add FP select. next up - divide! 
llvm-svn: 24346
 2005-11-14 01:17:30 +00:00
Duraid Madina
f5824e4fa3 fun with predicates! (add TRUNC i64->i1, AND i1 i1, fix XOR i1 i1) 
llvm-svn: 24175
 2005-11-04 00:57:56 +00:00
Duraid Madina
4adb8143ce add pattern to load constant 0 into a predicate reg 
llvm-svn: 24164
 2005-11-03 10:09:32 +00:00
Chris Lattner
cfb7edb4ed Fix a bug that prevented this pattern from matching 
llvm-svn: 24161
 2005-11-03 05:45:34 +00:00
Chris Lattner
04749a46a0 This works now 
llvm-svn: 24150
 2005-11-02 06:49:37 +00:00
Duraid Madina
94dd783c92 add support for SELECT to TargetSelectionDAG.td, add support for 
selecting ints to IA64, and a few other ia64 bits and pieces

llvm-svn: 24147
 2005-11-02 02:37:18 +00:00
Duraid Madina
7f2a0b1290 so tablegen was thinking I might want to convert FPs to predicates. 
clever little tablegen!

llvm-svn: 24133
 2005-11-01 03:32:15 +00:00
Duraid Madina
c754478fbe add support for int->FP and FP->int ops, and add ia64 patterns for these 
llvm-svn: 24132
 2005-11-01 03:07:25 +00:00
Duraid Madina
ba4b2d2a1b add zeroextend predicate->integer 
llvm-svn: 24131
 2005-11-01 01:29:55 +00:00
Duraid Madina
76abe0f46c add FP compares and implicit register defs to the dag isel 
llvm-svn: 24118
 2005-10-31 01:42:11 +00:00
Duraid Madina
5168a7dea5 fix some broken comparisons, this affected the Pattern isel too. 
llvm-svn: 24109
 2005-10-30 10:14:19 +00:00
Duraid Madina
9c1cbbe5d1 add some FP stuff, some mix.* stuff, and constant pool support to the 
DAG instruction selector, which should be destroyed one day (in the pattern
isel also) since ia64 can pack any constant in the instruction stream

llvm-svn: 24094
 2005-10-29 16:08:30 +00:00
Duraid Madina
6280da9a88 add shladd 
llvm-svn: 24080
 2005-10-29 04:13:40 +00:00
Duraid Madina
251185e626 DAG->DAG instruction selection for ia64! "hello world" works, not much else. 
use -enable-ia64-dag-isel to turn this on

TODO: delete lowering stuff from the pattern isel
    : get operations on predicate bits working
    : get other bits of pseudocode going
    : use sampo's mulh/mull-using divide-by-constant magic
    : *so* many patterns ("extr", "tbit" and "dep" will be fun :)
    : add FP
    : add a JIT!
    : get it working 100%

in short: this'll be happier in a couple of weeks, but it's here now so
the tester can make me feel guilty sooner.

OTHER: there are a couple of fixes to the pattern isel, in particular
making the linker happy with big blobs of fun like pypy.

llvm-svn: 24058
 2005-10-28 17:46:35 +00:00
Chris Lattner
cd5eeef9ee Give all operands names 
llvm-svn: 23357
 2005-09-14 21:11:13 +00:00
Chris Lattner
5194ff37c4 Mark some instructions as variable_ops, and PSEUDO_ALLOC as taking a GPR. 
I'm not convinced this is all of them,  but I can't do much testing, because
IA64 LLC crashes on big programs :(

llvm-svn: 22892
 2005-08-19 00:47:42 +00:00
Duraid Madina
b9062e56cf add the popcount instruction and support this in the isel 
the primary user of this will probably end up being find-first-set-bit/find-
last-set-bit, which i'll get around to...

llvm-svn: 21860
 2005-05-11 05:16:09 +00:00
Duraid Madina
0c40c548c0 print negative 64 bit immediates as negative numbers, makes things a little 
easier on the eyes, not that numbers like 18446744073709541376 are bad or
anything

llvm-svn: 21300
 2005-04-14 10:08:01 +00:00
Duraid Madina
b9d2d9ac63 * add the shladd instruction 
* fold left shifts of 1, 2, 3 or 4 bits into adds

  This doesn't save much now, but should get a serious workout once
  multiplies by constants get converted to shift/add/sub sequences.
  Hold on! :)

llvm-svn: 21282
 2005-04-13 06:12:04 +00:00
Chris Lattner
37712352c0 Make sure to realize that calls use their argument regs 
llvm-svn: 21248
 2005-04-12 15:12:19 +00:00
Duraid Madina
d2ae9221c7 assorted fixes: 
* clean up immediates (we use 14, 22 and 64 bit immediates now. sane.)
  * fold r0/f0/f1 registers into comparisons against 0/0.0/1.0
  * fix nasty thinko - didn't use two-address form of conditional add
    for extending bools to integers, so occasionally there would be
    garbage in the result. it's amazing how often zeros are just
    sitting around in registers ;) - this should fix a bunch of tests.

llvm-svn: 21221
 2005-04-11 05:55:56 +00:00
Duraid Madina
e7412561bf fix bogus division-by-power-of-2 (was wrong for negative input, adds extr insn) 
fix hack in division (clean up frcpa instruction)

llvm-svn: 21153
 2005-04-08 10:01:48 +00:00
Duraid Madina
5c4a7b68b3 add immediate forms of add, sub, shift 
llvm-svn: 21129
 2005-04-07 12:32:24 +00:00
Duraid Madina
1d156293cb add fms instruction 
llvm-svn: 21112
 2005-04-06 09:54:09 +00:00
Duraid Madina
d896a18d33 add implicit use op 
llvm-svn: 21074
 2005-04-04 04:50:57 +00:00
Duraid Madina
81675e4031 add fnegabs op 
llvm-svn: 21022
 2005-04-02 10:06:27 +00:00
Duraid Madina
333132da85 add support FNEG and FABS 
llvm-svn: 21012
 2005-04-02 05:18:38 +00:00
Duraid Madina
11ff0a2a5f add what we need to fudge a 'floating point conditional move', this is 
used to get FP div-by-zero working properly (shunt the right answer
depending on how frcpa sets its predicate output)

llvm-svn: 20954
 2005-03-31 07:32:32 +00:00
Duraid Madina
79022e1b87 and so it begins... 
PHASE 1: write instruction selector
PHASE 2: ???
PHASE 3: profit!

llvm-svn: 20652
 2005-03-17 18:17:03 +00:00