Craig Topper
2cd868184c
Add X86 BZHI instruction as well as BMI2 feature detection.
...
llvm-svn: 142122
2011-10-16 07:55:05 +00:00
Craig Topper
4c6357d4af
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
...
llvm-svn: 142105
2011-10-16 03:51:13 +00:00
Craig Topper
62e63d9bb9
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
...
llvm-svn: 142082
2011-10-15 20:46:47 +00:00
Bruno Cardoso Lopes
b3eab8c22d
Tidy up a bit more, fix tab and remove trailing whitespaces
...
llvm-svn: 140186
2011-09-20 21:45:26 +00:00
Bruno Cardoso Lopes
dab989502d
Tidy up code!
...
llvm-svn: 140183
2011-09-20 21:39:06 +00:00
Bruno Cardoso Lopes
9979e44f1b
Re-write part of VEX encoding logic, to be more easy to read! Also fix
...
a bug and add a testcase!
llvm-svn: 138123
2011-08-19 22:27:29 +00:00
Bruno Cardoso Lopes
306110c29a
Fix PR10677. Initial patch and idea by Peter Cooper but I've changed the
...
implementation!
llvm-svn: 138029
2011-08-19 02:23:56 +00:00
Evan Cheng
04762a3cf5
Emit an error is asm parser parsed X86_64 only registers, e.g. %rax, %sil.
...
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
2011-07-27 23:22:03 +00:00
Jeffrey Yasskin
8a0f9f17a3
Explicitly cast narrowing conversions inside {}s that will become errors in
...
C++0x.
llvm-svn: 136211
2011-07-27 06:22:51 +00:00
Evan Cheng
bbacc163bb
More refactoring.
...
llvm-svn: 135939
2011-07-25 19:33:48 +00:00
