1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-30 23:42:52 +01:00
Commit Graph

2629 Commits

Author SHA1 Message Date
Evan Cheng
cb2a0f392c Refactor scheduler code. Move register-reduction list scheduler to a
separate file. Added an initial implementation of top-down register pressure
reduction list scheduler.

llvm-svn: 28226
2006-05-11 23:55:42 +00:00
Evan Cheng
7028ff2e25 Set weight of zero length intervals to infinite to prevent them from being
spilled.

llvm-svn: 28220
2006-05-11 07:29:24 +00:00
Evan Cheng
da04c3aab4 Backing out previous check-in.
llvm-svn: 28219
2006-05-11 07:28:16 +00:00
Evan Cheng
03fa9eb65e If the live interval legnth is essentially zero, i.e. in every live range
the use follows def immediately, it doesn't make sense to spill it and
hope it will be easier to allocate for this LI.

llvm-svn: 28217
2006-05-10 22:30:41 +00:00
Evan Cheng
9f269c1bef Templatify RegReductionPriorityQueue
llvm-svn: 28212
2006-05-10 06:16:44 +00:00
Nate Begeman
3af196c9b2 Fix PR773
llvm-svn: 28207
2006-05-09 18:20:51 +00:00
Chris Lattner
486e0660b7 Fix a regression in my patch from last night that broke the llvmgcc4 build on
ppc

llvm-svn: 28205
2006-05-09 16:41:59 +00:00
Evan Cheng
1a8feb189e Add pseudo dependency to force a def&use operand to be scheduled last (unless
the distance between the def and another use is much longer). This is under
option control for now "-sched-lower-defnuse".

llvm-svn: 28201
2006-05-09 07:13:34 +00:00
Evan Cheng
3f72d2121b Debugging info
llvm-svn: 28200
2006-05-09 06:55:15 +00:00
Evan Cheng
aad3fe008e PR 770 - permit coallescing of registers in subset register classes.
llvm-svn: 28197
2006-05-09 06:37:48 +00:00
Chris Lattner
b7152b0b42 Implement MASM sections correctly, without a "has masm sections flag" and a bunch of special case code.
llvm-svn: 28194
2006-05-09 05:33:48 +00:00
Chris Lattner
28fe830b3b Oh yeah, there are two of these now, unify both.
llvm-svn: 28192
2006-05-09 05:24:50 +00:00
Chris Lattner
d2aea9851e Setting SwitchToSectionDirective properly in the MASM backend permits a bunch
of code to be unified.

llvm-svn: 28191
2006-05-09 05:23:12 +00:00
Chris Lattner
830bed591e Don't prefix section directives with a tab. Doing so causes blank lines to
be emitted to the .s file.

llvm-svn: 28189
2006-05-09 05:19:59 +00:00
Chris Lattner
baefeb1e09 Make the masm codepath work like the normal code path.
llvm-svn: 28188
2006-05-09 05:15:58 +00:00
Chris Lattner
6ede576b55 The MASM asmprinter has been fixed, these hacks are no longer needed.
llvm-svn: 28186
2006-05-09 05:13:34 +00:00
Chris Lattner
f45b6d5c08 Split SwitchSection into SwitchTo{Text|Data}Section methods.
llvm-svn: 28184
2006-05-09 04:59:56 +00:00
Chris Lattner
eed10e837c Make the case I just checked in stronger. Now we compile this:
short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

to:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test2:
        add r2, r3, r4
        extsh r2, r2
        srwi r2, r2, 1
        extsh r3, r2
        blr

llvm-svn: 28175
2006-05-08 21:18:59 +00:00
Chris Lattner
7b8a0cfff3 Implement and_sext.ll:test3, generating:
_test4:
        srawi r3, r3, 16
        blr

instead of:

_test4:
        srwi r2, r3, 16
        extsh r3, r2
        blr

for:

short test4(unsigned X) {
  return (X >> 16);
}

llvm-svn: 28174
2006-05-08 20:59:41 +00:00
Chris Lattner
4f66de151c Compile this:
short test4(unsigned X) {
  return (X >> 16);
}

to:

_test4:
        movl 4(%esp), %eax
        sarl $16, %eax
        ret

instead of:

_test4:
        movl $-65536, %eax
        andl 4(%esp), %eax
        sarl $16, %eax
        ret

llvm-svn: 28171
2006-05-08 20:51:54 +00:00
Chris Lattner
bbe4393bc4 Fold shifts with undef operands.
llvm-svn: 28167
2006-05-08 17:29:49 +00:00
Nate Begeman
1f359b07de Make emission of jump tables a bit less conservative; they are now required
to be only 31.25% dense, rather than 75% dense.

llvm-svn: 28165
2006-05-08 16:51:36 +00:00
Nate Begeman
b8e351aec5 Fix PR772
llvm-svn: 28161
2006-05-08 01:35:01 +00:00
Chris Lattner
f76c0b6662 Simplify some code, add a couple minor missed folds
llvm-svn: 28152
2006-05-06 23:06:26 +00:00
Chris Lattner
4a4cbde0bb constant fold sign_extend_inreg
llvm-svn: 28151
2006-05-06 23:05:41 +00:00
Chris Lattner
3d5d01a74b remove cases handled elsewhere
llvm-svn: 28150
2006-05-06 22:43:44 +00:00
Jeff Cohen
248e133255 Fix some loose ends in MASM support.
llvm-svn: 28148
2006-05-06 21:27:14 +00:00
Chris Lattner
ca06e2522e Use the new TargetLowering::ComputeNumSignBits method to eliminate
sign_extend_inreg operations.  Though ComputeNumSignBits is still rudimentary,
this is enough to compile this:

short test(short X, short x) {
  int Y = X+x;
  return (Y >> 1);
}
short test2(short X, short x) {
  int Y = (short)(X+x);
  return Y >> 1;
}

into:

_test:
        add r2, r3, r4
        srawi r3, r2, 1
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r3, r2, 1
        blr

instead of:

_test:
        add r2, r3, r4
        srawi r2, r2, 1
        extsh r3, r2
        blr
_test2:
        add r2, r3, r4
        extsh r2, r2
        srawi r2, r2, 1
        extsh r3, r2
        blr

llvm-svn: 28146
2006-05-06 09:30:03 +00:00
Chris Lattner
02d3258820 When inserting casts, be careful of where we put them. We cannot insert
a cast immediately before a PHI node.

This fixes Regression/CodeGen/Generic/2006-05-06-GEP-Cast-Sink-Crash.ll

llvm-svn: 28143
2006-05-06 09:10:37 +00:00
Chris Lattner
32e96402c0 Fold trunc(any_ext). This gives stuff like:
27,28c27
<       movzwl %di, %edi
<       movl %edi, %ebx
---
>       movw %di, %bx

llvm-svn: 28137
2006-05-05 22:56:26 +00:00
Chris Lattner
c912cf0b07 Shrink shifts when possible.
llvm-svn: 28136
2006-05-05 22:53:17 +00:00
Chris Lattner
06cb36074a Indent multiline asm strings more nicely
llvm-svn: 28132
2006-05-05 21:47:05 +00:00
Chris Lattner
4b581e4167 Fold (fpext (load x)) -> (extload x)
llvm-svn: 28130
2006-05-05 21:34:35 +00:00
Chris Lattner
229d3e3c2d More aggressively sink GEP offsets into loops. For example, before we
generated:

        movl 8(%esp), %eax
        movl %eax, %edx
        addl $4316, %edx
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, (%edx)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %edx
        movl %edx, 4460(%eax)
        ret
...

Now we generate:

        movl 8(%esp), %eax
        cmpb $1, %cl
        ja LBB1_2       #cond_false
LBB1_1: #cond_true
        movl L_QuantizationTables720$non_lazy_ptr, %ecx
        movl %ecx, 4316(%eax)
        movl L_QNOtoQuantTableShift720$non_lazy_ptr, %ecx
        movl %ecx, 4460(%eax)
        ret

... which uses one fewer register.

llvm-svn: 28129
2006-05-05 21:17:49 +00:00
Chris Lattner
d7637651b6 Fold some common code.
llvm-svn: 28124
2006-05-05 06:32:04 +00:00
Chris Lattner
584874682a Implement:
// fold (and (sext x), (sext y)) -> (sext (and x, y))
  // fold (or  (sext x), (sext y)) -> (sext (or  x, y))
  // fold (xor (sext x), (sext y)) -> (sext (xor x, y))
  // fold (and (aext x), (aext y)) -> (aext (and x, y))
  // fold (or  (aext x), (aext y)) -> (aext (or  x, y))
  // fold (xor (aext x), (aext y)) -> (aext (xor x, y))

llvm-svn: 28123
2006-05-05 06:31:05 +00:00
Chris Lattner
bec98440f4 Pull and through and/or/xor. This compiles some bitfield code to:
mov EAX, DWORD PTR [ESP + 4]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        or EDX, ECX
        and EDX, -2147483648
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        ret

instead of:

        sub ESP, 4
        mov DWORD PTR [ESP], ESI
        mov EAX, DWORD PTR [ESP + 8]
        mov ECX, DWORD PTR [EAX]
        mov EDX, ECX
        add EDX, EDX
        mov ESI, ECX
        and ESI, -2147483648
        and EDX, -2147483648
        or EDX, ESI
        and ECX, 2147483647
        or EDX, ECX
        mov DWORD PTR [EAX], EDX
        mov ESI, DWORD PTR [ESP]
        add ESP, 4
        ret

llvm-svn: 28122
2006-05-05 06:10:43 +00:00
Chris Lattner
02bb78abd3 Implement a variety of simplifications for ANY_EXTEND.
llvm-svn: 28121
2006-05-05 05:58:59 +00:00
Chris Lattner
53e8cbbb83 Factor some code, add these transformations:
// fold (and (trunc x), (trunc y)) -> (trunc (and x, y))
  // fold (or  (trunc x), (trunc y)) -> (trunc (or  x, y))
  // fold (xor (trunc x), (trunc y)) -> (trunc (xor x, y))

llvm-svn: 28120
2006-05-05 05:51:50 +00:00
Jeff Cohen
953baf0494 Fix VC++ compilation error.
llvm-svn: 28117
2006-05-05 01:47:05 +00:00
Chris Lattner
56694d0bb0 Sink noop copies into the basic block that uses them. This reduces the number
of cross-block live ranges, and allows the bb-at-a-time selector to always
coallesce these away, at isel time.

This reduces the load on the coallescer and register allocator.  For example
on a codec on X86, we went from:

   1643 asm-printer           - Number of machine instrs printed
    419 liveintervals         - Number of loads/stores folded into instructions
   1144 liveintervals         - Number of identity moves eliminated after coalescing
   1022 liveintervals         - Number of interval joins performed
    282 liveintervals         - Number of intervals after coalescing
   1304 liveintervals         - Number of original intervals
     86 regalloc              - Number of times we had to backtrack
1.90232 regalloc              - Ratio of intervals processed over total intervals
     40 spiller               - Number of values reused
    182 spiller               - Number of loads added
    121 spiller               - Number of stores added
    132 spiller               - Number of register spills
      6 twoaddressinstruction - Number of instructions commuted to coalesce
    360 twoaddressinstruction - Number of two-address instructions

to:

   1636 asm-printer           - Number of machine instrs printed
    403 liveintervals         - Number of loads/stores folded into instructions
   1155 liveintervals         - Number of identity moves eliminated after coalescing
   1033 liveintervals         - Number of interval joins performed
    279 liveintervals         - Number of intervals after coalescing
   1312 liveintervals         - Number of original intervals
     76 regalloc              - Number of times we had to backtrack
1.88998 regalloc              - Ratio of intervals processed over total intervals
      1 spiller               - Number of copies elided
     41 spiller               - Number of values reused
    191 spiller               - Number of loads added
    114 spiller               - Number of stores added
    128 spiller               - Number of register spills
      4 twoaddressinstruction - Number of instructions commuted to coalesce
    356 twoaddressinstruction - Number of two-address instructions

On this testcase, this change provides a modest reduction in spill code,
regalloc iterations, and total instructions emitted.  It increases the number
of register coallesces.

llvm-svn: 28115
2006-05-05 01:04:50 +00:00
Chris Lattner
db888e7880 Final pass of minor cleanups for MachineInstr
llvm-svn: 28110
2006-05-04 19:36:09 +00:00
Evan Cheng
ceb7645d40 Initial support for register pressure aware scheduling. The register reduction
scheduler can go into a "vertical mode" (i.e. traversing up the two-address
chain, etc.) when the register pressure is low.
This does seem to reduce the number of spills in the cases I've looked at. But
with x86, it's no guarantee the performance of the code improves.
It can be turned on with -sched-vertically option.

llvm-svn: 28108
2006-05-04 19:16:39 +00:00
Chris Lattner
32adc4592f Remove redundancy and a level of indirection when creating machine operands
llvm-svn: 28107
2006-05-04 19:14:44 +00:00
Chris Lattner
075404adaa Remove and simplify some more machineinstr/machineoperand stuff.
llvm-svn: 28105
2006-05-04 18:16:01 +00:00
Chris Lattner
eb41c99161 Rename MO_VirtualRegister -> MO_Register. Clean up immediate handling.
llvm-svn: 28104
2006-05-04 18:05:43 +00:00
Chris Lattner
685568510a Move some methods out of MachineInstr into MachineOperand
llvm-svn: 28102
2006-05-04 17:52:23 +00:00
Chris Lattner
97f1af2f14 There shalt be only one "immediate" operand type!
llvm-svn: 28099
2006-05-04 17:21:20 +00:00
Chris Lattner
51b0cac238 Change "value" in MachineOperand to be a GlobalValue, as that is the only
thing that can be in it.  Remove a dead method.

llvm-svn: 28098
2006-05-04 17:02:51 +00:00
Chris Lattner
a39a7f900f Remove a bunch more dead V9 specific stuff
llvm-svn: 28094
2006-05-04 01:26:39 +00:00
Chris Lattner
c779fca289 Remove a bunch more SparcV9 specific stuff
llvm-svn: 28093
2006-05-04 01:15:02 +00:00
Chris Lattner
ed58ec2a57 Remove some more V9-specific stuff.
llvm-svn: 28092
2006-05-04 00:49:59 +00:00
Chris Lattner
0f89e6b11d Remove some more unused stuff from MachineInstr that was leftover from V9.
llvm-svn: 28091
2006-05-04 00:44:25 +00:00
Chris Lattner
d36b66d6dc Suck block address tracking out of targets into the JIT Emitter. This
simplifies the MachineCodeEmitter interface just a little bit and makes
BasicBlocks work like constant pools and jump tables.

llvm-svn: 28082
2006-05-03 17:10:41 +00:00
Nate Begeman
95a4f191e0 Finish up the initial jump table implementation by allowing jump tables to
not be 100% dense.  Increase the minimum threshold for the number of cases
in a switch statement from 4 to 6 in order to create a jump table.

llvm-svn: 28079
2006-05-03 03:48:02 +00:00
Evan Cheng
2922daab4b Bottom up register pressure reduction work: clean up some hacks and enhanced
the heuristic to further reduce spills for several test cases. (Note, it may
not necessarily translate to runtime win!)

llvm-svn: 28076
2006-05-03 02:10:45 +00:00
Owen Anderson
71bc529dfa Refactor TargetMachine, pushing handling of TargetData into the target-specific subclasses. This has one caller-visible change: getTargetData() now returns a pointer instead of a reference.
This fixes PR 759.

llvm-svn: 28074
2006-05-03 01:29:57 +00:00
Chris Lattner
06ccac43d7 Change the BasicBlockAddrs map to be a vector, indexed by MBB number.
llvm-svn: 28069
2006-05-03 00:32:55 +00:00
Chris Lattner
2bf37af52d Several related changes:
1. Change several methods in the MachineCodeEmitter class to be pure virtual.
2. Suck emitConstantPool/initJumpTableInfo into startFunction, removing them
   from the MachineCodeEmitter interface, and reducing the amount of target-
   specific code.
3. Change the JITEmitter so that it allocates constantpools and jump tables
   *right* next to the functions that they belong to, instead of in a separate
   pool of memory.  This makes all memory for a function be contiguous, and
   means the JITEmitter only tracks one block of memory now.

llvm-svn: 28065
2006-05-02 23:22:24 +00:00
Chris Lattner
8054cd3830 Do not make the JIT memory manager manage the memory for globals. Instead
just have the JIT malloc them.

llvm-svn: 28062
2006-05-02 21:57:51 +00:00
Chris Lattner
055baf5c7b Refactor the machine code emitter interface to pull the pointers for the current
code emission location into the base class, instead of being in the derived classes.

This change means that low-level methods like emitByte/emitWord now are no longer
virtual (yaay for speed), and we now have a framework to support growable code
segments.  This implements feature request #1 of PR469.

llvm-svn: 28059
2006-05-02 18:27:26 +00:00
Nate Begeman
2a81b6be22 Print function number instead of name
llvm-svn: 28057
2006-05-02 17:36:46 +00:00
Chris Lattner
5c1abc2b94 Remove dead method
llvm-svn: 28055
2006-05-02 17:20:28 +00:00
Chris Lattner
bb8c8b5d9d Remove the debug machine code emitter. The "FilePrinterEmitter" is more
useful for debugging.

llvm-svn: 28051
2006-05-02 16:59:24 +00:00
Nate Begeman
05174045df Extend printBasicBlockLabel a bit so that it can be used to print all
basic block labels, consolidating the code to do so in one place for each
target.

llvm-svn: 28050
2006-05-02 05:37:32 +00:00
Jeff Cohen
a35a8a5f9c De-virtualize SwitchSection.
llvm-svn: 28047
2006-05-02 03:58:45 +00:00
Jeff Cohen
b257253098 De-virtualize EmitZeroes.
llvm-svn: 28046
2006-05-02 03:46:13 +00:00
Jeff Cohen
ec0f5808a1 Make Intel syntax mode friendlier to Microsoft ML assembler (still needs more work).
llvm-svn: 28044
2006-05-02 01:16:28 +00:00
Chris Lattner
c2914c8ac5 Fix a latent bug that my spiller patch last week exposed: we were leaving
instructions in the virtregfolded map that were deleted.  Because they
were deleted, newly allocated instructions could end up at the same address,
magically finding themselves in the map.  The solution is to remove entries
from the map when we delete the instructions.

llvm-svn: 28041
2006-05-01 22:03:24 +00:00
Chris Lattner
a9f3c7c50a When promoting a load to a reg-reg copy, where the load was a previous
instruction folded with spill code, make sure the remove the load from
the virt reg folded map.

llvm-svn: 28040
2006-05-01 21:17:10 +00:00
Chris Lattner
befcd1e76d Remove previous patch, which wasn't quite right.
llvm-svn: 28039
2006-05-01 21:16:03 +00:00
Evan Cheng
44e851f6ec Dis-favor stores more
llvm-svn: 28035
2006-05-01 09:20:44 +00:00
Evan Cheng
494e47d755 Bottom up register-pressure reduction scheduler now pushes store operations
up the schedule. This helps code that looks like this:

loads ...
computations (first set) ...
stores (first set) ...
loads
computations (seccond set) ...
stores (seccond set) ...

Without this change, the stores and computations are more likely to
interleave:

loads ...
loads ...
computations (first set) ...
computations (second set) ...
computations (first set) ...
stores (first set) ...
computations (second set) ...
stores (stores set) ...

This can increase the number of spills if we are unlucky.

llvm-svn: 28033
2006-05-01 09:14:40 +00:00
Evan Cheng
94264c7c90 Didn't mean ScheduleDAGList.cpp to make the last checkin.
llvm-svn: 28030
2006-05-01 08:56:34 +00:00
Evan Cheng
ef706b77c4 Remove temp. option -spiller-check-liveout, it didn't cause any failure nor performance regressions.
llvm-svn: 28029
2006-05-01 08:54:57 +00:00
Chris Lattner
bce271e829 Format #APP lines a bit nicer
llvm-svn: 28026
2006-05-01 04:11:03 +00:00
Evan Cheng
02e72f8f55 Local spiller kills a store if the folded restore is turned into a copy.
But this is incorrect if the spilled value live range extends beyond the
current BB.
It is currently controlled by a temporary option -spiller-check-liveout.

llvm-svn: 28024
2006-04-30 08:41:47 +00:00
Chris Lattner
6ce6942d21 Remove a bogus transformation. This fixes SingleSource/UnitTests/2006-01-23-InitializedBitField.c
with some changes I have to the new CFE.

llvm-svn: 28022
2006-04-28 23:33:20 +00:00
Evan Cheng
9f21c2daf4 Remove the temporary option: -no-isel-fold-inflight
llvm-svn: 28012
2006-04-28 18:54:11 +00:00
Evan Cheng
f843942504 TargetLowering::LowerArguments should return a VBIT_CONVERT of
FORMAL_ARGUMENTS SDOperand in the return result vector.

llvm-svn: 28009
2006-04-28 05:25:15 +00:00
Chris Lattner
4e783a3101 Mapping of physregs can make it so that the designated and input physregs are
the same.  In this case, don't emit a noop copy.

llvm-svn: 28008
2006-04-28 04:43:18 +00:00
Evan Cheng
ff5a88b62e Added a temporary option -no-isel-fold-inflight to control whether a "inflight"
node can be folded.

llvm-svn: 28003
2006-04-28 02:09:19 +00:00
Chris Lattner
85a24e23a2 When we have a two-address instruction where the input cannot be clobbered
and is already available, instead of falling back to emitting a load, fall
back to emitting a reg-reg copy.  This generates significantly better code
for some SSE testcases, as SSE has lots of two-address instructions and
none of them are read/modify/write.  As one example, this change does:

        pshufd %XMM5, XMMWORD PTR [%ESP + 84], 255
        xorps %XMM2, %XMM5
        cmpltps %XMM1, %XMM0
-       movaps XMMWORD PTR [%ESP + 52], %XMM0
-       movapd %XMM6, XMMWORD PTR [%ESP + 52]
+       movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 68]
        movapd XMMWORD PTR [%ESP + 52], %XMM6
        movaps %XMM6, %XMM0
        cmpltps %XMM6, XMMWORD PTR [%ESP + 36]
        cmpltps %XMM3, %XMM0
-       movaps XMMWORD PTR [%ESP + 20], %XMM0
-       movapd %XMM7, XMMWORD PTR [%ESP + 20]
+       movaps %XMM7, %XMM0
        cmpltps %XMM7, XMMWORD PTR [%ESP + 4]
        movapd XMMWORD PTR [%ESP + 20], %XMM7
        cmpltps %XMM4, %XMM0

... which is far better than a store followed by a load!

llvm-svn: 28001
2006-04-28 01:46:50 +00:00
Evan Cheng
a6081bc674 Insert a VBIT_CONVERT between a FORMAL_ARGUMENT node and its vector uses
(VAND, VADD, etc.). Legalizer will assert otherwise.

llvm-svn: 27991
2006-04-27 08:29:42 +00:00
Chris Lattner
3b27c1bd33 Fix Regression/CodeGen/Generic/2006-04-26-SetCCAnd.ll and
PR748.

llvm-svn: 27987
2006-04-27 05:01:07 +00:00
Evan Cheng
b54140b0d6 Don't forget return void.
llvm-svn: 27974
2006-04-25 23:03:35 +00:00
Nate Begeman
7bb910dbe7 Fix the updating of the machine CFG when a PHI node was in a successor of
the jump table's range check block.  This re-enables 100% dense jump tables
by default on PPC & x86

llvm-svn: 27952
2006-04-23 06:26:20 +00:00
Nate Begeman
f86709e9e2 Code cleanup associated with jump tables, thanks to Chris for noticing
these.

llvm-svn: 27950
2006-04-22 23:52:35 +00:00
Nate Begeman
6cfb33a42c Turn of jump tables for a bit, there are still some issues to work out with
updating the machine CFG.

llvm-svn: 27949
2006-04-22 23:51:56 +00:00
Nate Begeman
7ed816f900 JumpTable support! What this represents is working asm and jit support for
x86 and ppc for 100% dense switch statements when relocations are non-PIC.
This support will be extended and enhanced in the coming days to support
PIC, and less dense forms of jump tables.

llvm-svn: 27947
2006-04-22 18:53:45 +00:00
Chris Lattner
8f7c394f3a The BFS scheduler is apparently nondeterminstic (causes many llvmgcc bootstrap
miscompares).  Switch RISC targets to use the list-td scheduler, which isn't.

llvm-svn: 27933
2006-04-21 17:16:16 +00:00
Chris Lattner
3b9a7570cb Fix a couple more memory issues
llvm-svn: 27930
2006-04-21 15:32:26 +00:00
Chris Lattner
2ae3ed5e1a Fix a really subtle and obnoxious memory bug that caused issues with an
llvm-gcc4 boostrap.  Whenever a node is deleted by the dag combiner, it
*must* be returned by the visit function, or the dag combiner will not
know that the node has been processed (and will, e.g., send it to the
target dag combine xforms).

llvm-svn: 27922
2006-04-20 23:55:59 +00:00
Chris Lattner
04a8496ef0 This field no longer exists
llvm-svn: 27899
2006-04-20 18:32:41 +00:00
Chris Lattner
a6a6ac15af Remove some of the obvious V9-specific cruft
llvm-svn: 27893
2006-04-20 18:08:53 +00:00
Evan Cheng
618314ed2f Turn a VAND into a VECTOR_SHUFFLE is applicable.
DAG combiner can turn a VAND V, <-1, 0, -1, -1>, i.e. vector clear elements,
into a vector shuffle with a zero vector. It only does so when TLI tells it
the xform is profitable.

llvm-svn: 27874
2006-04-20 08:56:16 +00:00
Chris Lattner
fa2e364d9c Implement folding of a bunch of binops with undef
llvm-svn: 27863
2006-04-20 05:39:12 +00:00
Chris Lattner
a1cf724536 Simplify some code
llvm-svn: 27846
2006-04-19 23:17:50 +00:00
Chris Lattner
8c8f1e35c9 Fix handling of calls in functions that use vectors. This fixes a crash on
the code in GCC PR26546.

llvm-svn: 27780
2006-04-17 22:10:08 +00:00
Chris Lattner
5f5a9cc8ea Add a MachineInstr::eraseFromParent convenience method.
llvm-svn: 27775
2006-04-17 21:35:41 +00:00