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3 Commits

Author SHA1 Message Date
Matt Arsenault
1adcdc6e96 AMDGPU: Add sdst operand to VOP2b instructions 
The VOP3 encoding of these allows any SGPR pair for the i1
output, but this was forced before to always use vcc.
This doesn't yet try to use this, but does add the operand
to the definitions so the main change is adding vcc to the
output of the VOP2 encoding.

llvm-svn: 246358
 2015-08-29 07:16:50 +00:00
Tom Stellard
d96b39afde AMDPGU/SI: Negative offsets aren't allowed in MUBUF's vaddr operand 
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11226

llvm-svn: 242434
 2015-07-16 19:40:09 +00:00
Tom Stellard
3f1708598e R600 -> AMDGPU rename 
llvm-svn: 239657
 2015-06-13 03:28:10 +00:00