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Commit Graph

6 Commits

Author SHA1 Message Date
Jakob Stoklund Olesen
005ed7e482 Don't try to be clever, just preserve the target's allocation order.
The order of registers returned by getCalleeSavedRegs is used to lay out
the fixed stack slots for CSRs. Some targets like their CSRs used from
one end, and some targets want them used from the other end.

When computing an allocation order, simply preserve the relative
ordering of CSRs that the target specifies in its allocation order.
Reordering CSRs would break some targets, ARM in particular.

We still place volatiles before the CSRs, providing slightly better
results with different calling conventions.

llvm-svn: 132680
2011-06-06 16:36:30 +00:00
Jakob Stoklund Olesen
e345312955 Preserve the original ordering when a CSR has multiple aliases.
Previously, these aliases would be ordered alphabetically. (BH, BL)

Print out the computed allocation orders.

llvm-svn: 132580
2011-06-03 20:34:50 +00:00
Jakob Stoklund Olesen
52c6a75ee3 Just use a SmallVector.
I was confused whether new uint8_t[] would zero-initialize the returned
array, and it seems that so is gcc-4.0.

This should fix the test failures on darwin 9.

llvm-svn: 132500
2011-06-02 22:22:43 +00:00
Benjamin Kramer
e149500163 Start with a zeroed CSRNum map.
Found by valgrind.

llvm-svn: 132457
2011-06-02 12:07:44 +00:00
Jakob Stoklund Olesen
a8db700d44 Initialize members to fix problem found by valgrind.
llvm-svn: 132456
2011-06-02 05:43:49 +00:00
Jakob Stoklund Olesen
24726cedf4 Add a RegisterClassInfo class that lazily caches information about
register classes.

It provides information for each register class that cannot be
determined statically, like:

- The number of allocatable registers in a class after filtering out the
  reserved and invalid registers.

- The preferred allocation order with registers that overlap callee-saved
  registers last.

- The last callee-saved register that overlaps a given physical register.

This information usually doesn't change between functions, so it is
reused for compiling multiple functions when possible.  The many
possible combinations of reserved and callee saves registers makes it
unfeasible to compute this information statically in TableGen.

Use RegisterClassInfo to count available registers in various heuristics
in SimpleRegisterCoalescing, making the pass run 4% faster.

llvm-svn: 132450
2011-06-02 02:19:35 +00:00