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Commit Graph

120496 Commits

Author SHA1 Message Date
David Majnemer
d34b4538b5 [IR] Cleanup some formatting issues in the EH instructions
No functionality change is intended.

llvm-svn: 244399
2015-08-08 17:41:21 +00:00
Rafael Espindola
ead34eeb8c Return early on error. Should fix the asan bots.
llvm-svn: 244397
2015-08-08 14:54:09 +00:00
Craig Topper
09426f8318 [X86] Add ADX and RDSEED to Skylake processor.
llvm-svn: 244396
2015-08-08 07:31:15 +00:00
Craig Topper
f9b8d39b42 Add SlowBTMem to Sandy Bridge and newer Intel CPUs. Reading through Agner Fog's table suggests there have been no improvements to these processors relative to Westmere for bit test instructions.
llvm-svn: 244395
2015-08-08 07:20:04 +00:00
David Majnemer
eabf812a59 [InstCombine] Don't try to sink EH pad instructions
Found by inspection, this change should not effect the existing
landingpad behavior.

llvm-svn: 244391
2015-08-08 03:51:49 +00:00
NAKAMURA Takumi
1cc5e3f1ba 244368: Fix a comment line introduced in r244368. [-Wdocumentation]
llvm-svn: 244388
2015-08-08 01:34:20 +00:00
David Majnemer
08eb997d7e [IR] Stop hacking around a bug in GCC 4.5
GCC 4.5 miscompiled this aspect of LLVM.  We support a minimum version
of 4.7.

llvm-svn: 244387
2015-08-08 01:33:30 +00:00
Craig Topper
5033eede06 Add model numbers for Skylake CPUs and an additional Broadwell model.
llvm-svn: 244385
2015-08-08 01:29:15 +00:00
Craig Topper
b81b70117f Add Intel family 6 model 93 as Silvermont.
llvm-svn: 244384
2015-08-08 01:16:05 +00:00
Tom Stellard
15de4ba0ef AMDGPU/SI: Another attempt to fix Windows bots broken by r244372
llvm-svn: 244383
2015-08-08 01:11:07 +00:00
Matt Arsenault
a7a9e929b5 Remove unnecessary includes
llvm-svn: 244382
2015-08-08 00:41:53 +00:00
Matt Arsenault
04b53db7bf AMDGPU: Implement AMDGPUOperand::print()
llvm-svn: 244381
2015-08-08 00:41:51 +00:00
Matt Arsenault
b0ba266970 AMDGPU/SI: Remove VCCReg
llvm-svn: 244380
2015-08-08 00:41:48 +00:00
Matt Arsenault
ec3023a130 AMDGPU/SI: Remove source uses of VCCReg
llvm-svn: 244379
2015-08-08 00:41:45 +00:00
Rafael Espindola
f6876bec4e Delete dead code. NFC.
llvm-svn: 244378
2015-08-08 00:25:57 +00:00
Tom Stellard
cd6ab5c821 AMDGPU/SI: Attempt to fix Windows bots broken by r244372
llvm-svn: 244376
2015-08-08 00:17:59 +00:00
Rafael Espindola
088669ce42 Convert getSymbolSection to return an ErrorOr.
This function can actually fail since the symbol contains an index to the
section and that can be invalid.

llvm-svn: 244375
2015-08-07 23:27:14 +00:00
Sanjay Patel
d517a7b7ab add a missing regression test for a DAGCombiner FDIV optimization
There's no test for this transform in any backend. Discovered
while debugging fast-math-flag propagation in the DAG (r244053).

llvm-svn: 244373
2015-08-07 23:19:41 +00:00
Tom Stellard
6f30f702e1 AMDGPU: Add pass to lower OpenCL image and sampler arguments.
The pass adds new kernel arguments for image attributes, and
resolves calls to dummy attribute and resource id getter functions.

Patch by: Zoltan Gilian

llvm-svn: 244372
2015-08-07 23:19:30 +00:00
James Y Knight
3d1f40b9ec [SPARC] Disable unsupported ExecutionEngine tests, and XFAIL a couple
of DebugInfo tests.

llvm-svn: 244371
2015-08-07 23:01:16 +00:00
Adam Nemet
c67a08de7f [LAA] Remove unused pointer partition argument from getNumberOfChecks, NFC
This is unused after filtering checks was moved to the clients.

As a result, we can just return the number of the checks in the
precomputed set.

llvm-svn: 244369
2015-08-07 22:44:21 +00:00
Adam Nemet
36760f098d [LAA] Make the set of runtime checks part of the state of LAA, NFC
This is the full set of checks that clients can further filter. IOW,
it's client-agnostic.  This makes LAA complete in the sense that it now
provides the two main results of its analysis precomputed:

1. memory dependences via getDepChecker().getInsterestingDependences()
2. run-time checks via getRuntimePointerCheck().getChecks()

However, as a consequence we now compute this information pro-actively.
Thus if the client decides to skip the loop based on the dependences
we've computed the checks unnecessarily.  In order to see whether this
was a significant overhead I checked compile time on SPEC2k6 LTO bitcode
files.  The change was in the noise.

The checks are generated in canCheckPtrAtRT, at the same place where we
used to call groupChecks to merge checks.

llvm-svn: 244368
2015-08-07 22:44:15 +00:00
Quentin Colombet
d05bd6348b [AArch64][LoadStoreOptimizer] Turn a test into an assert. NFC.
At this point the given Opc must be valid, otherwise we should
not look for a matching pair to form paired load or store.

Thanks to Chad to point out this piece of code!

llvm-svn: 244366
2015-08-07 22:40:51 +00:00
Tom Stellard
dfc5991339 AMDGPU/SI: Use InstAlias instead of MnemonicAlias for VOPC instructions
Summary:
With InstAlias, we don't need to print the _e32 portion of the mnemonic
when we print the $dst operand.  This change makes it possible to
include vcc in the asm string when we switch VOPC over to having
implicit vcc defs.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11813

llvm-svn: 244362
2015-08-07 22:00:56 +00:00
Sanjay Patel
d2b53ea457 redo r244360 (tighten checks...) after specifying triple
llvm-svn: 244361
2015-08-07 21:42:24 +00:00
Sanjay Patel
5037c7782e tighten checks using update_llc_test_checks.py
llvm-svn: 244360
2015-08-07 21:38:53 +00:00
Alex Lorenz
7b9ddd3d95 MIR Serialization: Serialize the base alignment for the machine memory operands.
llvm-svn: 244357
2015-08-07 20:48:30 +00:00
Alex Lorenz
39e2231276 MIR Serialization: Serialize the offsets for the machine memory operands.
llvm-svn: 244356
2015-08-07 20:26:52 +00:00
Alex Lorenz
7a90618f38 MIR Parser: Extract the parsing of the operand's offset into a new method. NFC.
This commit extract the code that parses the 64-bit offset from the method
'parseOperandsOffset' to a new method 'parseOffset' so that we can reuse it
when parsing the offset for the machine memory operands.

llvm-svn: 244355
2015-08-07 20:21:00 +00:00
Matt Arsenault
b7690a5199 AMDGPU: Assume SMRD access for constant address space
Since r243294 these are selected to SMRD and
moved later if required.

llvm-svn: 244354
2015-08-07 20:18:34 +00:00
Rafael Espindola
731b9ea15f Don't look for a SHT_DYNSYM in the ELFFile's constructor.
Yet another step in not having it scan every section.

llvm-svn: 244353
2015-08-07 20:11:08 +00:00
Craig Topper
ff53ab3a44 Add Intel family 6 model 90 as Silvermont. Fixes PR24392.
llvm-svn: 244352
2015-08-07 20:09:42 +00:00
Rafael Espindola
246909bb95 Remove the symbol iteration functions that don't take a symbol table.
Another step in making ELFFile's constructor not iterate over all sections.

llvm-svn: 244351
2015-08-07 20:07:27 +00:00
Adam Nemet
59fd1cc3c9 [LAA] Remove unused pointer partition argument from print(), NFC
This is now handled in the client.  No need for LAA to provide this
variant.

llvm-svn: 244349
2015-08-07 19:44:48 +00:00
Chen Li
ef70e358a3 [ConstantFoldTerminator] Preserve make.implicit metadata when converting SwitchInst to BranchInst
Summary: llvm::ConstantFoldTerminator function can convert SwitchInst with single case (and default) to a conditional BranchInst. This patch adds support to preserve make.implicit metadata on this conversion.

Reviewers: sanjoy, weimingz, chenli

Subscribers: mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D11841

llvm-svn: 244348
2015-08-07 19:30:12 +00:00
Frederic Riss
f618de09d4 [MCDwarf] Use more idiomatic [u]int8_t types.
llvm-svn: 244347
2015-08-07 19:19:44 +00:00
Simon Pilgrim
c31bcce147 [InstCombine] Fix SSE2/AVX2 vector logical shift by constant
This patch fixes the sse2/avx2 vector shift by constant instcombine call to correctly deal with the fact that the shift amount is formed from the entire lower 64-bit and not just the lowest element as it currently assumes.

e.g.

%1 = tail call <4 x i32> @llvm.x86.sse2.psrl.d(<4 x i32> %v, <4 x i32> <i32 15, i32 15, i32 15, i32 15>)

In this case, (V)PSRLD doesn't perform a lshr by 15 but in fact attempts to shift by 64424509455 ((15 << 32) | 15) - giving a zero result.

In addition, this review also recognizes shift-by-zero from a ConstantAggregateZero type (PR23821).

Differential Revision: http://reviews.llvm.org/D11760

llvm-svn: 244341
2015-08-07 18:22:50 +00:00
Cong Hou
ce64545c16 NFC.
Use a parent class to avoid reduncant code when specializing GraphTraits for T and const T.

llvm-svn: 244340
2015-08-07 18:04:17 +00:00
Nico Weber
b3a3522ac1 Add functions to save and restore the PrettyStackTrace state.
PrettyStackTraceHead is a LLVM_THREAD_LOCAL, which means it's just a global
in LLVM_ENABLE_THREADS=NO builds.  If a CrashRecoveryContext is used with
code that uses PrettyStackEntries, and a crash happens, PrettyStackTraceHead is
currently not reset to its pre-crash value.  These functions make it possible
to add a cleanup to such code that does this.

(Not reseting the value then causes the assert in ~PrettyStackTraceEntry() to
fire if the code outside of the CrashRecoveryContext also uses
PrettyStackEntries -- for example, clang when building a module.)

Part of PR11974.

llvm-svn: 244338
2015-08-07 17:47:03 +00:00
Nico Weber
198bc9060d Add a comment.
llvm-svn: 244337
2015-08-07 17:32:06 +00:00
Rafael Espindola
0fb3af3648 Delete dead code. NFC.
llvm-svn: 244335
2015-08-07 17:06:05 +00:00
Chad Rosier
defd3944ce [ARM] Remove an unused reference to MachineRegisterInfo. NFC.
llvm-svn: 244334
2015-08-07 17:02:29 +00:00
Rafael Espindola
186d9c2b83 Don't use a DenseMap to handle SHT_SYMTAB_SHNDX.
It is already a convenient table.

llvm-svn: 244333
2015-08-07 16:51:44 +00:00
Tom Stellard
162c8c165f AMDGPU/SI: Use correct encoding of vopc for VI in the assembler
Summary: We were using the SI encoding for VI.

Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11812

llvm-svn: 244332
2015-08-07 16:45:33 +00:00
Tom Stellard
83c4e6365d AMDGPU/SI: Add VI checks to vop3 assembler tests
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11811

llvm-svn: 244331
2015-08-07 16:45:30 +00:00
Eric Christopher
65dbfa2fff We're actually -Wmissing-field-initializers clean thanks to the cmake
build so check and turn on -Wmissing-field-initializers. While there,
reorganize the conditional warning code based on compiler to be a bit
more obvious and inside a switch statement.

llvm-svn: 244330
2015-08-07 16:44:47 +00:00
Rafael Espindola
cd0f8af304 Delete dead typedef. NFC.
llvm-svn: 244328
2015-08-07 16:36:47 +00:00
Frederic Riss
dfb0d2fac5 Use 'signed char' instead of 'char'
Hope this fixes the s390 and aarch64 bots.

llvm-svn: 244327
2015-08-07 16:31:59 +00:00
Rafael Espindola
e75ec1768a add missing tests files
llvm-svn: 244323
2015-08-07 15:35:49 +00:00
Tom Stellard
ae73825453 AMDGPU/SI: v_mac_legacy_f32 does not exist on VI
Reviewers: arsenm

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D11810

llvm-svn: 244322
2015-08-07 15:34:30 +00:00