Hal Finkel
42a487282a
Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore.
...
Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.
llvm-svn: 153821
2012-04-01 04:44:16 +00:00
Jia Liu
b077b6085d
Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore.
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llvm-svn: 150878
2012-02-18 12:03:15 +00:00
Evan Cheng
39c462b4f1
Add support to model pipeline bypass / forwarding.
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llvm-svn: 115005
2010-09-28 23:50:49 +00:00
Anton Korobeynikov
e325c693a5
Make processor FUs unique for given itinerary. This extends the limit of 32
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FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.
llvm-svn: 101754
2010-04-18 20:31:01 +00:00
Chris Lattner
ad9a6ccb83
Remove attribution from file headers, per discussion on llvmdev.
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llvm-svn: 45418
2007-12-29 20:36:04 +00:00
Jim Laskey
514a74d946
Added InstrSchedClass to each of the PowerPC Instructions.
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Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.
llvm-svn: 23830
2005-10-19 19:51:16 +00:00
Jim Laskey
0918760dec
Push processor descriptions to the top of target and add command line info.
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llvm-svn: 23820
2005-10-19 13:34:52 +00:00
Jim Laskey
da117aa6d3
Simple edits; remove unimplimented cases and clarify long haul SLU cases.
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llvm-svn: 23788
2005-10-18 16:59:23 +00:00
Jim Laskey
610af28ca0
Checking in first round of scheduling tablegen files. Not tied in as yet.
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llvm-svn: 23786
2005-10-18 16:23:40 +00:00
