Owen Anderson
64c500c7dd
Fix decoding support for STREXD and LDREXD.
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llvm-svn: 137356
2011-08-11 21:34:58 +00:00
Jim Grosbach
5c12d41c95
ARM STRH assembly parsing and encoding.
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llvm-svn: 137353
2011-08-11 21:17:22 +00:00
Owen Anderson
4618d77bcd
Fix decoding for indexed STRB and LDRB. Fixes <rdar://problem/9926161>.
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llvm-svn: 137347
2011-08-11 20:47:56 +00:00
Jim Grosbach
15351f4f22
Tidy up. Remove unused template parameter.
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llvm-svn: 137345
2011-08-11 20:41:13 +00:00
Owen Anderson
1ec4fcb5d3
Improve operand validation for Thumb2 addressing modes.
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llvm-svn: 137344
2011-08-11 20:40:40 +00:00
Jim Grosbach
81b2835f83
ARM STRD assembly parsing and encoding.
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llvm-svn: 137342
2011-08-11 20:28:23 +00:00
Owen Anderson
73e7d34732
Continue to tighten decoding by performing more operand validation.
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llvm-svn: 137340
2011-08-11 20:21:46 +00:00
Jim Grosbach
92a220276d
Tidy up.
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llvm-svn: 137339
2011-08-11 20:13:35 +00:00
Jim Grosbach
bfc85134c2
ARM STRBT assembly parsing and encoding.
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llvm-svn: 137337
2011-08-11 20:04:56 +00:00
Jim Grosbach
e6bd3a1ab8
ARM STR(immediate) assembly parsing and encoding.
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llvm-svn: 137331
2011-08-11 19:22:40 +00:00
Owen Anderson
63ccfdccd1
Tighten decoding of addrmode2 instructions to reject more UNPREDICTABLE cases.
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llvm-svn: 137325
2011-08-11 19:00:18 +00:00
Owen Anderson
decc5fcced
Tighten operand decoding of addrmode2 instruction. The offset register cannot be PC.
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llvm-svn: 137323
2011-08-11 18:55:42 +00:00
Owen Anderson
707fcaca0e
Correct immediate range for shifter operands. Patch by James Molloy, with additional encoding fixes added by me.
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llvm-svn: 137322
2011-08-11 18:41:59 +00:00
Owen Anderson
8d6b9f063f
Improve error checking in the new ARM disassembler. Patch by James Molloy.
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llvm-svn: 137320
2011-08-11 18:24:51 +00:00
Jim Grosbach
9717a9c0d3
ARM push of a single register encodes as pre-indexed STR.
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Per the ARM ARM, a 'push' of a single register encodes as an STR,
not an STM.
llvm-svn: 137318
2011-08-11 18:07:11 +00:00
Jim Grosbach
abaaf4513f
ARM pop of a single register encodes as post-indexed LDR.
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Per the ARM ARM, a 'pop' of a single register encodes as an LDR,
not an LDM.
llvm-svn: 137316
2011-08-11 17:35:48 +00:00
Jim Grosbach
5322f1ea74
ARM LDRT assembly parsing and encoding.
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llvm-svn: 137282
2011-08-10 23:43:54 +00:00
Jim Grosbach
9fd458fd63
Tidy up. 80 columns.
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llvm-svn: 137277
2011-08-10 23:23:47 +00:00
Jim Grosbach
e0ccd6b34e
ARM LDRH(immediate) assembly parsing and encoding support.
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llvm-svn: 137260
2011-08-10 22:42:16 +00:00
Jim Grosbach
4ad2dc8bb2
ARM LDRD(register) assembly parsing and encoding.
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Add support for literal encoding of #-0 along the way.
llvm-svn: 137254
2011-08-10 21:56:18 +00:00
Jim Grosbach
e19952cfbb
Fix typo. Not quite sure how that slipped in there.
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llvm-svn: 137245
2011-08-10 20:49:18 +00:00
Jim Grosbach
bbef0044c8
ARM LDRD(immediate) assembly parsing and encoding support.
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llvm-svn: 137244
2011-08-10 20:29:19 +00:00
Owen Anderson
0fde7a84ee
Add initial support for decoding NEON instructions in Thumb2 mode.
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llvm-svn: 137236
2011-08-10 19:01:10 +00:00
Owen Anderson
59d627c17a
Tabs --> spaces.
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llvm-svn: 137225
2011-08-10 17:38:05 +00:00
Owen Anderson
0819cf208f
Cleanups based on Nick Lewycky's feedback.
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llvm-svn: 137224
2011-08-10 17:36:48 +00:00
Owen Anderson
0d68079e26
Rewrite some ARM InstrInfo functions to be most accepting of arbitrary register subclasses. Hopefully this fixes some buildbots.
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llvm-svn: 137223
2011-08-10 17:21:20 +00:00
Rafael Espindola
45cd7316b5
Add support for the R and Q constraints.
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llvm-svn: 137217
2011-08-10 16:26:42 +00:00
Owen Anderson
87b5ce880a
Push GPRnopc through a large number of instruction definitions to tighten operand decoding.
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llvm-svn: 137189
2011-08-10 00:03:03 +00:00
Jakob Stoklund Olesen
3ab24a9494
Promote VMOVS to VMOVD when possible.
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On Cortex-A8, we use the NEON v2f32 instructions for f32 arithmetic. For
better latency, we also send D-register copies down the NEON pipeline by
translating them to vorr instructions.
This patch promotes even S-register copies to D-register copies when
possible so they can also go down the NEON pipeline. Example:
vldr.32 s0, LCPI0_0
loop:
vorr d1, d0, d0
loop2:
...
vadd.f32 d1, d1, d16
The vorr instruction looked like this after regalloc:
%S2<def> = COPY %S0, %D1<imp-def>
Copies involving odd S-registers, and copies that don't define the full
D-register are left alone.
llvm-svn: 137182
2011-08-09 23:41:44 +00:00
Owen Anderson
b717d71aa1
Tighten operand checking of register-shifted-register operands.
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llvm-svn: 137180
2011-08-09 23:33:27 +00:00
Owen Anderson
62faf296dd
Tighten operand checking on memory barrier instructions.
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llvm-svn: 137176
2011-08-09 23:25:42 +00:00
Owen Anderson
869ce85500
Tighten operand checking on CPS instructions.
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llvm-svn: 137172
2011-08-09 23:05:39 +00:00
Owen Anderson
8ad37f68a2
Create a new register class for the set of all GPRs except the PC. Use it to tighten our decoding of BFI.
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llvm-svn: 137168
2011-08-09 22:48:45 +00:00
Benjamin Kramer
ca48bdfd5b
ARM Disassembler: sign extend branch immediates.
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Not sure about BLXi, but this is what the old disassembler did.
llvm-svn: 137156
2011-08-09 22:02:50 +00:00
Owen Anderson
4232cf9141
Silence an false-positive warning.
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llvm-svn: 137154
2011-08-09 21:38:14 +00:00
Owen Anderson
09d5afaefa
Don't generate the old-style disassembler in CMake builds either.
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llvm-svn: 137153
2011-08-09 21:36:11 +00:00
Benjamin Kramer
ed2b147693
The new ARM disassembler disassembles "bx lr" as a special BX_ret instruction so target specific analysis isn't needed anymore.
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llvm-svn: 137151
2011-08-09 21:34:19 +00:00
Owen Anderson
2443a29f51
Don't continue generating the old-style decoder file.
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llvm-svn: 137150
2011-08-09 21:30:29 +00:00
Jim Grosbach
d47981e34a
ARM fix typo in pre-indexed store lowering.
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rdar://9915869
llvm-svn: 137148
2011-08-09 21:22:41 +00:00
Owen Anderson
433265b44e
Attempt to fix CMake build.
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llvm-svn: 137147
2011-08-09 21:09:59 +00:00
Owen Anderson
2aa4c7e391
Tighten Thumb1 branch predicate decoding.
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llvm-svn: 137146
2011-08-09 21:07:45 +00:00
Owen Anderson
ffe1c55752
Replace the existing ARM disassembler with a new one based on the FixedLenDecoderEmitter.
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This new disassembler can correctly decode all the testcases that the old one did, though
some "expected failure" testcases are XFAIL'd for now because it is not (yet) as strict in
operand checking as the old one was.
llvm-svn: 137144
2011-08-09 20:55:18 +00:00
Renato Golin
dc14179294
Emitting ARM build attributes and values as ULEB, rather than char.
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llvm-svn: 137115
2011-08-09 09:50:10 +00:00
Jim Grosbach
d6da18cf19
ARM parsing and encoding for LDRBT instruction.
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Fix the instruction representation to correctly only allow post-indexed form.
Add tests.
llvm-svn: 137074
2011-08-08 23:28:47 +00:00
Owen Anderson
5b0611a4eb
Thumb1 BL instructions encoding 22 bits of displacement, not 21.
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llvm-svn: 137073
2011-08-08 23:25:22 +00:00
Jakob Stoklund Olesen
c239010f17
Implement isLoadFromStackSlotPostFE and isStoreToStackSlotPostFE for ARM.
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They improve the verbose assembly.
llvm-svn: 137069
2011-08-08 21:45:32 +00:00
Jim Grosbach
ffac5ceead
ARM load/store label parsing.
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Allow labels for load/store instructions when parsing. There's encoding
issues, still, so this doesn't work all the way through, yet.
llvm-svn: 137064
2011-08-08 20:59:31 +00:00
Owen Anderson
e4638b5b2d
Fix encodings for Thumb ASR and LSR immediate operands. They encode the range 1-32, with 32 encoded as 0.
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llvm-svn: 137062
2011-08-08 20:42:17 +00:00
Eli Friedman
7a34419c6f
Fix up the patterns for SXTB, SXTH, UXTB, and UXTH so that they are correctly active without HasT2ExtractPack. PR10611.
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llvm-svn: 137061
2011-08-08 19:49:37 +00:00
Benjamin Kramer
8c3f23ec80
Add MCInstrAnalysis class. This allows the targets to specify own versions of MCInstrDescs functions.
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- Add overrides for ARM.
- Teach llvm-objdump to use this instead of plain MCInstrDesc.
llvm-svn: 137059
2011-08-08 18:56:44 +00:00