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5 Commits

Author SHA1 Message Date
Daniel Sanders
21c7c7cd9b [mips][msa] Added support for build_vector for v4f32 and v2f64. 
llvm-svn: 192699
 2013-10-15 13:14:41 +00:00
Daniel Sanders
8c83ddcdd2 [mips][msa] Implemented insert_vector_elt for v4f32 and v2f64. 
For v4f32 and v2f64, INSERT_VECTOR_ELT is matched by a pseudo-insn which is
later expanded to appropriate insve.[wd] insns.

llvm-svn: 191515
 2013-09-27 12:31:32 +00:00
Daniel Sanders
0bb1b5a37f [mips][msa] Implemented extract_vector_elt for v4f32 or v2f64 
For v4f32 and v2f64, EXTRACT_VECTOR_ELT is matched by a pseudo-insn which may
be expanded to subregister copies and/or instructions as appropriate.

llvm-svn: 191514
 2013-09-27 12:17:32 +00:00
Daniel Sanders
d13fea547a [mips][msa] MSA requires FR=1 mode (64-bit FPU register file). Report fatal error when using it in FR=0 mode. 
llvm-svn: 191498
 2013-09-27 10:08:31 +00:00
Daniel Sanders
d3c403c386 [mips][msa] Implemented build_vector using ldi, fill, and custom SelectionDAG nodes (VSPLAT and VSPLATD) 
Note: There's a later patch on my branch that re-implements this to select
build_vector without the custom SelectionDAG nodes. The future patch avoids
the constant-folding problems stemming from the custom node (i.e. it doesn't
need to re-implement all the DAG combines related to BUILD_VECTOR).

Changes to MIPS specific SelectionDAG nodes:
* Added VSPLAT
    This is a special case of BUILD_VECTOR that covers the case the
    BUILD_VECTOR is a splat operation.
* Added VSPLATD
    This is a special case of VSPLAT that handles the cases when v2i64 is legal

llvm-svn: 191191
 2013-09-23 12:02:46 +00:00