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Commit Graph

40 Commits

Author SHA1 Message Date
Chris Lattner
55043ef46a fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel 
like detangling).   Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.

llvm-svn: 114471
2010-09-21 20:31:19 +00:00
Chris Lattner
8df3ffd7ac zap dead code.
llvm-svn: 113073
2010-09-04 18:12:00 +00:00
Jakob Stoklund Olesen
b3539aa611 Merge the SystemZ subreg_even32 SubRegIndex into subreg_32bit. The SubRegIndices
were overspecified when inheriting sub-subregisters, for instance:

R0Q:subreg_even32 = R0Q:subreg_32bit = R0Q:subreg_even:subreg_32bit.

This meant that composeSubRegIndices(subreg_even, subreg_32bit) was ambiguous.

llvm-svn: 105063
2010-05-28 23:48:29 +00:00
Jakob Stoklund Olesen
56e4442b2c Use enums instead of literals for SystemZ subregisters
llvm-svn: 104612
2010-05-25 17:04:18 +00:00
Dan Gohman
a0f855157e Use const qualifiers with TargetLowering. This eliminates several
const_casts, and it reinforces the design of the Target classes being
immutable.

SelectionDAGISel::IsLegalToFold is now a static member function, because
PIC16 uses it in an unconventional way. There is more room for API
cleanup here.

And PIC16's AsmPrinter no longer uses TargetLowering.

llvm-svn: 101635
2010-04-17 15:26:15 +00:00
Chris Lattner
1707a88a2c Sink InstructionSelect() out of each target into SDISel, and rename it
DoInstructionSelection.  Inline "SelectRoot" into it from DAGISelHeader.
Sink some other stuff out of DAGISelHeader into SDISel.

Eliminate the various 'Indent' stuff from various targets, which dates
to when isel was recursive.

 17 files changed, 114 insertions(+), 430 deletions(-)

llvm-svn: 97555
2010-03-02 06:34:30 +00:00
Evan Cheng
b5fe25544c Split SelectionDAGISel::IsLegalAndProfitableToFold to
IsLegalToFold and IsProfitableToFold. The generic version of the later simply checks whether the folding candidate has a single use.

This allows the target isel routines more flexibility in deciding whether folding makes sense. The specific case we are interested in is folding constant pool loads with multiple uses.

llvm-svn: 96255
2010-02-15 19:41:07 +00:00
Chris Lattner
7acf9be6c4 move target-independent opcodes out of TargetInstrInfo
into TargetOpcodes.h.  #include the new TargetOpcodes.h
into MachineInstr.  Add new inline accessors (like isPHI())
to MachineInstr, and start using them throughout the 
codebase.

llvm-svn: 95687
2010-02-09 19:54:29 +00:00
Dan Gohman
9bcfdf98f1 Change SelectCode's argument from SDValue to SDNode *, to make it more
clear what information these functions are actually using.

This is also a micro-optimization, as passing a SDNode * around is
simpler than passing a { SDNode *, int } by value or reference.

llvm-svn: 92564
2010-01-05 01:24:18 +00:00
Anton Korobeynikov
3915cf5ef4 Fix invalid chain folding for memory variant of sdiv / udiv
llvm-svn: 92472
2010-01-04 10:31:54 +00:00
Dan Gohman
eec0f1c506 Remove uninteresting and confusing debug output.
llvm-svn: 86149
2009-11-05 18:47:09 +00:00
Dan Gohman
0c4e55a2f8 Rename getTargetNode to getMachineNode, for consistency with the
naming scheme used in SelectionDAG, where there are multiple kinds
of "target" nodes, but "machine" nodes are nodes which represent
a MachineInstr.

llvm-svn: 82790
2009-09-25 18:54:59 +00:00
Daniel Dunbar
411094cde6 Fix some refactos for iostream changes (in -Asserts mode).
- The world needs better C++ refactoring tools, can I get an Amen!?

llvm-svn: 79843
2009-08-23 08:50:52 +00:00
Chris Lattner
bd73307361 eliminate uses of cerr()
llvm-svn: 79834
2009-08-23 07:05:07 +00:00
Chris Lattner
26ec3291f0 eliminate the last DOUTs from the targets.
llvm-svn: 79833
2009-08-23 06:49:22 +00:00
Owen Anderson
48f2f0ae72 Split EVT into MVT and EVT, the former representing _just_ a primitive type, while
the latter is capable of representing either a primitive or an extended type.

llvm-svn: 78713
2009-08-11 20:47:22 +00:00
Owen Anderson
b4bce99769 Rename MVT to EVT, in preparation for splitting SimpleValueType out into its own struct type.
llvm-svn: 78610
2009-08-10 22:56:29 +00:00
Daniel Dunbar
fd7e588f92 Fix 'may be used uninitialized' warning.
- Anton, please review.

llvm-svn: 76144
2009-07-17 02:19:26 +00:00
Anton Korobeynikov
c66cf22284 Unbreak
llvm-svn: 76064
2009-07-16 14:36:52 +00:00
Anton Korobeynikov
94f250ff30 Fix logic inversion for RI-mode address selection
llvm-svn: 76052
2009-07-16 14:31:14 +00:00
Anton Korobeynikov
60427c0b64 Unbreak mvi and friends - emit only 'significant' part of the operand
llvm-svn: 76041
2009-07-16 14:26:38 +00:00
Anton Korobeynikov
3e670f38f9 Provide consistent subreg idx scheme. This (hopefully) fixes remaining divide problems
llvm-svn: 76011
2009-07-16 14:18:17 +00:00
Anton Korobeynikov
bf722c6946 Use divide single for 32 bit signed divides
llvm-svn: 76010
2009-07-16 14:17:52 +00:00
Anton Korobeynikov
6ff1411adf Remove redundand register move
llvm-svn: 76004
2009-07-16 14:14:54 +00:00
Anton Korobeynikov
f48e88136e Properly handle divides. As a bonus - implement memory versions of them.
llvm-svn: 76003
2009-07-16 14:14:33 +00:00
Anton Korobeynikov
e6b7c15a63 32 bit shifts have only 12 bit displacements
llvm-svn: 76000
2009-07-16 14:13:24 +00:00
Anton Korobeynikov
6d0c8510ab Typos
llvm-svn: 75991
2009-07-16 14:10:35 +00:00
Anton Korobeynikov
6c1091e7f3 Consolidate reg-imm / reg-reg-imm address mode selection logic in one place.
llvm-svn: 75990
2009-07-16 14:10:17 +00:00
Anton Korobeynikov
9a1ad49207 Add support for 12 bit displacements
llvm-svn: 75988
2009-07-16 14:09:35 +00:00
Anton Korobeynikov
0fd61ed25a 32-bit ri addressing mode has only 12-bit displacement
llvm-svn: 75973
2009-07-16 14:03:41 +00:00
Anton Korobeynikov
6d15e5c657 Swap the order of imm and idx field for rri addrmode in order to make handling of rri and ri addrmodes common
llvm-svn: 75937
2009-07-16 13:48:42 +00:00
Anton Korobeynikov
c0374ea3e6 Do not truncate sign bits for negative imms
llvm-svn: 75936
2009-07-16 13:48:23 +00:00
Anton Korobeynikov
5e1fa67a23 Add address computation stuff
llvm-svn: 75935
2009-07-16 13:47:59 +00:00
Anton Korobeynikov
b88da5c190 Add stores and truncstores
llvm-svn: 75931
2009-07-16 13:45:00 +00:00
Anton Korobeynikov
b262cec2d0 Add patterns for various extloads
llvm-svn: 75930
2009-07-16 13:44:30 +00:00
Anton Korobeynikov
58f9ca9055 Do some heroic rri address matching (shamelessly stolen from x86 backend). Not tested though.
llvm-svn: 75929
2009-07-16 13:44:00 +00:00
Anton Korobeynikov
f080a4a0bd Add shifts and reg-imm address matching
llvm-svn: 75927
2009-07-16 13:43:18 +00:00
Anton Korobeynikov
f63382b52b Add bunch of reg-imm movs
llvm-svn: 75921
2009-07-16 13:34:50 +00:00
Anton Korobeynikov
dcc7d19ef3 Provide masked reg-imm 'or' and 'and'
llvm-svn: 75919
2009-07-16 13:33:57 +00:00
Anton Korobeynikov
8155f0cbaa Let's start another backend :)
llvm-svn: 75909
2009-07-16 13:27:25 +00:00