RPCS3/llvm-mirror
1
0
Fork 0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-11-25 12:12:47 +01:00
Code Issues Projects Releases Wiki Activity
64,913 Commits 4 Branches 5 Tags 704 MiB
662193bddc
Commit Graph

10881 Commits

Author SHA1 Message Date
Cameron Esfahani
662193bddc Fix PR8201: Update the code to call via X86::CALL64pcrel32 in the 64-bit case. 
llvm-svn: 114597
 2010-09-22 22:35:21 +00:00
Rafael Espindola
3cfff6e0c5 Avoid some Mach-O specific alignment being done on ELF. 
llvm-svn: 114594
 2010-09-22 22:27:05 +00:00
Rafael Espindola
a2d73f0a38 Correctly align bss. 
llvm-svn: 114556
 2010-09-22 17:43:04 +00:00
Mikhail Glushenkov
dba65f26d2 llvmc: Support '-emit-llvm -S' with -opt. 
llvm-svn: 114541
 2010-09-22 09:00:41 +00:00
Chris Lattner
f90b2a5a26 fix rdar://8456371 - Handle commutable instructions written backward. 
llvm-svn: 114536
 2010-09-22 06:26:39 +00:00
Chris Lattner
1864d6728d Fix an inconsistency in the x86 backend that led it to reject "calll foo" on 
x86-32: 32-bit calls were named "call" not "calll".  64-bit calls were correctly
named "callq", so this only impacted x86-32.

This fixes rdar://8456370 - llvm-mc rejects 'calll'

This also exposes that mingw/64 is generating a 32-bit call instead of a 64-bit call,
I will file a bugzilla.

llvm-svn: 114534
 2010-09-22 05:49:14 +00:00
Chris Lattner
1ff3935290 fix rdar://8456412 - llvm-mc crash in encoder on "mov %rdx, %cr8" 
Teaching the code generator about CR8-15, how to rex them up, etc.

llvm-svn: 114533
 2010-09-22 05:29:50 +00:00
Chris Lattner
1c5e55f787 fix rdar://8456417 - llvm-mc can't do basic math 
llvm-svn: 114532
 2010-09-22 05:05:16 +00:00
Chris Lattner
77d657ae6a add the missing aliases for fp stack cmovs, rdar://8456391 
llvm-svn: 114531
 2010-09-22 04:56:20 +00:00
Chris Lattner
26d11d7501 reimplement elf TLS support in terms of addressing modes, eliminating SegmentBaseAddress. 
llvm-svn: 114529
 2010-09-22 04:39:11 +00:00
Chris Lattner
2e61516c5a Fix rdar://8456364 - llvm-mc rejects '%CS' 
llvm-svn: 114528
 2010-09-22 04:11:10 +00:00
Chris Lattner
2d350c46e2 fix rdar://8456389 - llvm-mc mismatch with 'as' on 'fstp' 
-This line, and those below, will be ignored--

M    test/MC/AsmParser/X86/x86_instructions.s
M    lib/Target/X86/AsmParser/X86AsmParser.cpp

llvm-svn: 114527
 2010-09-22 04:04:03 +00:00
Chris Lattner
f43f09693e fix rdar://8456361 - llvm-mc rejects 'rep movsd' 
llvm-svn: 114526
 2010-09-22 03:50:32 +00:00
Chris Lattner
d42791ad4a linux has a different stack alignment than the mac, relax this a bit. 
llvm-svn: 114519
 2010-09-22 00:46:26 +00:00
Chris Lattner
e52da86fab give VZEXT_LOAD a memory operand, it now works with segment registers. 
llvm-svn: 114515
 2010-09-22 00:34:38 +00:00
Chris Lattner
706b9206da revert r114386 now that address modes work correctly, we get a nice 
call through gs-relative memory now.

llvm-svn: 114510
 2010-09-22 00:11:31 +00:00
Chris Lattner
f9861312cb give LCMPXCHG_DAG[8] a memory operand, allowing it to work with addrspace 256/257 
llvm-svn: 114508
 2010-09-21 23:59:42 +00:00
Chris Lattner
08b4ce2b31 filecheckize 
llvm-svn: 114507
 2010-09-21 23:57:27 +00:00
Evan Cheng
1d58965067 OptimizeCompareInstr should avoid iterating pass the beginning of the MBB when the 'and' instruction is after the comparison. 
llvm-svn: 114506
 2010-09-21 23:49:07 +00:00
Owen Anderson
d9fd152c3a Enable target-specific mul-lowering on ARM, even at -Os. Remove a test that this makes 
irrelevant, but add a new test for the new, improved functionality.

llvm-svn: 114494
 2010-09-21 22:51:46 +00:00
Devang Patel
53b709a85c Use FileCheck 
llvm-svn: 114475
 2010-09-21 20:50:32 +00:00
Owen Anderson
97a8fdc19c When adding the carry bit to another value on X86, exploit the fact that the carry-materialization 
(sbbl x, x) sets the registers to 0 or ~0.  Combined with two's complement arithmetic, we can fold
the intermediate AND and the ADD into a single SUB.

This fixes <rdar://problem/8449754>.

llvm-svn: 114460
 2010-09-21 18:41:19 +00:00
Mikhail Glushenkov
35e2ea68d2 llvmc: Allow multiple output languages. 
llvm-svn: 114433
 2010-09-21 14:59:42 +00:00
Chris Lattner
ecdba24738 fix rdar://8453210, a crash handling a call through a GS relative load. 
For now, just disable folding the load into the call.

llvm-svn: 114386
 2010-09-21 03:37:00 +00:00
Rafael Espindola
02af3cdd58 Implement support for .local and its "interesting" interactions with .comm. 
llvm-svn: 114382
 2010-09-21 00:24:38 +00:00
Evan Cheng
1ce02d180e Enable machine sinking critical edge splitting. e.g. 
define double @foo(double %x, double %y, i1 %c) nounwind {
  %a = fdiv double %x, 3.2
  %z = select i1 %c, double %a, double %y
  ret double %z
}

Was:
_foo:
        divsd   LCPI0_0(%rip), %xmm0
        testb   $1, %dil
        jne     LBB0_2
        movaps  %xmm1, %xmm0
LBB0_2:
        ret

Now:
_foo:
        testb   $1, %dil
        je      LBB0_2
        divsd   LCPI0_0(%rip), %xmm0
        ret
LBB0_2:
        movaps  %xmm1, %xmm0
        ret

This avoids the divsd when early exit is taken.
rdar://8454886

llvm-svn: 114372
 2010-09-20 22:52:00 +00:00
Owen Anderson
b8811b9ed9 CombinerAA is now reordering these stores. 
llvm-svn: 114354
 2010-09-20 20:56:29 +00:00
Owen Anderson
fc94b337eb When TCO is turned on, it is possible to end up with aliasing FrameIndex's. Therefore, 
CombinerAA cannot assume that different FrameIndex's never alias, but can instead use
MachineFrameInfo to get the actual offsets of these slots and check for actual aliasing.

This fixes CodeGen/X86/2010-02-19-TailCallRetAddrBug.ll and CodeGen/X86/tailcallstack64.ll
when CombinerAA is enabled, modulo a different register allocation sequence.

llvm-svn: 114348
 2010-09-20 20:39:59 +00:00
Jim Grosbach
cf90f8beb1 Simplify ARM callee-saved register handling by removing the distinction 
between the high and low registers for prologue/epilogue code. This was
a Darwin-only thing that wasn't providing a realistic benefit anymore.
Combining the save areas simplifies the compiler code and results in better
ARM/Thumb2 codegen.

For example, previously we would generate code like:
        push    {r4, r5, r6, r7, lr}
        add     r7, sp, #12
        stmdb   sp!, {r8, r10, r11}
With this change, we combine the register saves and generate:
        push    {r4, r5, r6, r7, r8, r10, r11, lr}
        add     r7, sp, #12

rdar://8445635

llvm-svn: 114340
 2010-09-20 19:32:20 +00:00
Rafael Espindola
78fc1f7f66 Produce a R_X86_64_32 when the value is >=0. 
llvm-svn: 114339
 2010-09-20 19:20:47 +00:00
NAKAMURA Takumi
a8d8b5f3c3 test/CodeGen/X86: Add explicit triplet -mtriple=i686-linux to 3 tests incompatible to Win32 codegen. 
r114297 raises 3 failures. They might fail also on mingw.

llvm-svn: 114317
 2010-09-19 21:58:55 +00:00
Eric Christopher
2901b19344 Add the exit instruction to the PTX target. 
Patch by Che-Liang Chiou <clchiou@gmail.com>!

llvm-svn: 114294
 2010-09-18 18:52:28 +00:00
Rafael Espindola
9c3a9bf8aa Make sure the STT_FILE symbol is the first one in the symbol table. 
llvm-svn: 114285
 2010-09-18 15:03:21 +00:00
Owen Anderson
015641f659 Invert the logic of reachesChainWithoutSideEffects(). What we want to check is that there is 
NO path to the destination containing side effects, not that SOME path contains no side effects.
In  practice, this only manifests with CombinerAA enabled, because otherwise the chain has little
to no branching, so "any" is effectively equivalent to "all".

llvm-svn: 114268
 2010-09-18 04:45:14 +00:00
Rafael Espindola
32e423fe2b Add test that was missing in my previous commit. 
llvm-svn: 114248
 2010-09-18 00:37:27 +00:00
Dan Gohman
e96841854e Attempt to XFAIL this test on arm-linux, which is inexplicably failing. 
llvm-svn: 114241
 2010-09-18 00:04:37 +00:00
Benjamin Kramer
1cad9b6521 Fix vmov.f64 disassembly on targets where sizeof(long) != 8. 
llvm-svn: 114240
 2010-09-17 23:48:07 +00:00
Bob Wilson
670e1915c0 Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64 
value should be in GPRs when it's going to be used as a scalar, and we use
VMOVRRD to make that happen, but if the value is converted back to a vector
we need to fold to a simple bit_convert.  Radar 8407927.

llvm-svn: 114233
 2010-09-17 22:59:05 +00:00
Jim Grosbach
8ae5cfffdd Teach the (non-MC) instruction printer to use the cannonical names for push/pop, 
and shift instructions on ARM. Update the tests to match.

llvm-svn: 114230
 2010-09-17 22:36:38 +00:00
Evan Cheng
8c2bde65f0 Teach machine sink to 
1) Do forward copy propagation. This makes it easier to estimate the cost of the
   instruction being sunk.
2) Break critical edges on demand, including cases where the value is used by
   PHI nodes.
Critical edge splitting is not yet enabled by default.

llvm-svn: 114227
 2010-09-17 22:28:18 +00:00
Jim Grosbach
d2cf0742a4 Update tests to handle MC-inst instruction printing of shift operations. The 
legacy asm printer uses instructions of the form, "mov r0, r0, lsl #3", while
the MC-instruction printer uses the form "lsl r0, r0, #3". The latter mnemonic
is correct and preferred according the ARM documentation (A8.6.98). The former
are pseudo-instructions for the latter.

llvm-svn: 114221
 2010-09-17 21:58:46 +00:00
Jim Grosbach
b86aebe2b7 FileCheck-ize 
llvm-svn: 114218
 2010-09-17 21:46:16 +00:00
Jim Grosbach
b21c19d666 Move thumb2 tests to the thumb2 directory 
llvm-svn: 114206
 2010-09-17 20:34:09 +00:00
Jim Grosbach
026811c86f tweak test to check instructions rather than relying on the comment string 
llvm-svn: 114204
 2010-09-17 20:27:26 +00:00
Dan Gohman
4487f42592 Fix this test to avoid an "inexact" fold. 
llvm-svn: 114202
 2010-09-17 20:25:43 +00:00
Dan Gohman
aaed2c137f Avoid emitting a PIC base register if no PIC addresses are needed. 
This fixes rdar://8396318.

llvm-svn: 114201
 2010-09-17 20:24:24 +00:00
Jim Grosbach
fd21b4bb15 tweak test to check instructions rather than relying on the comment string 
llvm-svn: 114200
 2010-09-17 20:21:03 +00:00
Jim Grosbach
5ca55bd98b tweak test to check instructions rather than relying on the comment string 
llvm-svn: 114199
 2010-09-17 20:17:41 +00:00
Dan Gohman
0e6744d219 Fix this test so that folding doesn't depend on a potentially 
"inexact" result.

llvm-svn: 114198
 2010-09-17 20:15:53 +00:00
Chris Lattner
4bce01542c fix rdar://8444631 - encoder crash on 'enter' 
What a weird instruction.

llvm-svn: 114190
 2010-09-17 18:02:29 +00:00