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Commit Graph

156034 Commits

Author SHA1 Message Date
Simon Pilgrim
612223546a [SelectionDAG] Add support for INSERT_SUBVECTOR to computeKnownBits
llvm-svn: 316847
2017-10-28 22:10:40 +00:00
Simon Pilgrim
a7fd382c14 [X86][SSE] Combine 128-bit target shuffles to PACKSS/PACKUS.
llvm-svn: 316845
2017-10-28 20:51:27 +00:00
Simon Pilgrim
70261faac1 [X86][SSE] Split off matchVectorShuffleWithPACK. NFCI.
Split matchVectorShuffleWithPACK from lowerVectorShuffleWithPACK so that we can reuse it for target shuffle combines

llvm-svn: 316844
2017-10-28 20:27:22 +00:00
Craig Topper
2cb3773070 [X86] Fix a mistake in the X86ISelDAGToDAG.cpp code for MUL8r/IMUL8r.
I think this code is unreachable due to some promotions that occur elsewhere. I'll look into that to be sure, but for now I thought I should at least fix the obvious typo.

llvm-svn: 316840
2017-10-28 19:56:57 +00:00
Craig Topper
54a084614e [X86] Replace some default cases in X86SelectShift with llvm_unreachable.
llvm-svn: 316839
2017-10-28 19:56:56 +00:00
Saleem Abdulrasool
92084746fc ADT: add a helper to check if the Triple is ARM64
Add a trivial helper for checking if the architecture is AArch64 Little
Endian or Big Endian.

llvm-svn: 316837
2017-10-28 19:15:05 +00:00
Sanjay Patel
ab3266d1be [SimplifyCFG] use pass options and remove the latesimplifycfg pass
This is no-functional-change-intended.

This is repackaging the functionality of D30333 (defer switch-to-lookup-tables) and 
D35411 (defer folding unconditional branches) with pass parameters rather than a named
"latesimplifycfg" pass. Now that we have individual options to control the functionality,
we could decouple when these fire (but that's an independent patch if desired). 

The next planned step would be to add another option bit to disable the sinking transform
mentioned in D38566. This should also make it clear that the new pass manager needs to
be updated to limit simplifycfg in the same way as the old pass manager.

Differential Revision: https://reviews.llvm.org/D38631

llvm-svn: 316835
2017-10-28 18:43:07 +00:00
Simon Pilgrim
ceb99fd633 [X86][SSE] Rename truncateVectorCompareWithPACKSS to truncateVectorWithPACKSS. NFC.
We no longer rely on the vector source being a comparison result, just have sufficient sign bits.

llvm-svn: 316834
2017-10-28 17:59:56 +00:00
Craig Topper
5107597825 [X86] Correct the alignments on the aligned test cases in fast-isel-vecload.ll to make sure they test selection of aligned loads.
llvm-svn: 316833
2017-10-28 17:37:51 +00:00
Simon Pilgrim
a120e99e55 [SelectionDAG] Support 'bit preserving' floating points bitcasts on computeKnownBits/ComputeNumSignBits
For cases where we know the floating point representations match the bitcasted integer equivalent, allow bitcasting to these types.

This is especially useful for the X86 floating point compare results which return all/zero bits but as a floating point type.

Differential Revision: https://reviews.llvm.org/D39289

llvm-svn: 316831
2017-10-28 14:27:53 +00:00
Craig Topper
262a2f9079 [X86] Add avx command lines to fast-isel-constpool.ll to improve coverage.
llvm-svn: 316829
2017-10-28 06:31:48 +00:00
Craig Topper
cf03911459 [X86] Use update_llc_test_checks.py to regenerate fast-isel-constpool.ll
llvm-svn: 316828
2017-10-28 06:31:46 +00:00
Craig Topper
9e1f2067a3 [X86] Add a fast-isel test for the i8 pseudo cmov.
llvm-svn: 316827
2017-10-28 06:10:03 +00:00
Craig Topper
67b2246759 [X86] Remove unneeded MVT::i1 related code from fast isel.
llvm-svn: 316825
2017-10-28 05:52:23 +00:00
Haicheng Wu
1f0902194e [ConstantFold] Fix a crash when folding a GEP that has vector index
LLVM crashes when factoring out an out-of-bound index into preceding dimension
and the preceding dimension uses vector index.  Simply bail out now when this
case happens.

Differential Revision: https://reviews.llvm.org/D38677

llvm-svn: 316824
2017-10-28 02:27:14 +00:00
Craig Topper
0be01a1e27 [X86] Add avx command lines to two fast-isel tests to get coverage of selecting vucomiss/vucomisd.
The selection of these shows up as a code coverage hole when looking at the llvm-cov link on llvm.org

llvm-svn: 316823
2017-10-28 02:03:59 +00:00
Craig Topper
c1a0d0cd5f [X86] Use update_llc_test_checks.py to regenerate fast-isel-select-cmov2.ll
llvm-svn: 316822
2017-10-28 02:03:58 +00:00
Craig Topper
8fabf09e88 [PartialInlineLibCalls] Teach PartialInlineLibCalls to honor nobuiltin, properly check the function signature, and check TLI::has
Summary:
We shouldn't do this transformation if the function is marked nobuitlin.

We were only checking that the return type is floating point, we really should be checking the argument types and argument count as well. This can be accomplished by using the other version of getLibFunc that takes the Function and not just the name.

We should also be checking TLI::has since sqrtf is a macro on Windows.

Fixes PR32559.

Reviewers: hfinkel, spatel, davide, efriedma

Reviewed By: davide, efriedma

Subscribers: efriedma, llvm-commits, eraman

Differential Revision: https://reviews.llvm.org/D39381

llvm-svn: 316819
2017-10-28 00:36:58 +00:00
Eugene Zelenko
df1c971e39 [ADT] Fix some Clang-tidy modernize and Include What You Use warnings; other minor fixes (NFC).
llvm-svn: 316818
2017-10-28 00:24:26 +00:00
Tom Stellard
1745f38fdd AMDGPU/GlobalISel: Mark 32-bit G_FADD as legal
Reviewers: arsenm

Reviewed By: arsenm

Subscribers: kzhuravl, wdng, nhaehnle, yaxunl, rovka, kristof.beyls, igorb, dstuttard, tpr, t-tye, llvm-commits

Differential Revision: https://reviews.llvm.org/D38439

llvm-svn: 316815
2017-10-27 23:57:41 +00:00
Bob Haarman
82955ffac2 [support] remove tautological comparison in Support/Windows/Path.inc
Summary:
The removed code checks that we are able to handle a 64-bit number, but
the code we're calling takes two dwords (for a total of 64 bits), so this
is always true.

Reviewers: zturner, rnk, majnemer, compnerd

Reviewed By: zturner

Subscribers: amccarth, hiraditya, lebedev.ri, llvm-commits

Differential Revision: https://reviews.llvm.org/D39263

llvm-svn: 316814
2017-10-27 23:41:17 +00:00
Jake Ehrlich
cafca24ac3 Revert "Add support for writing 64-bit symbol tables for archives when offsets become too large for 32-bit"
This reverts commit r316805.

llvm-svn: 316813
2017-10-27 23:39:31 +00:00
Jake Ehrlich
f6b4e47d10 Add support for writing 64-bit symbol tables for archives when offsets become too large for 32-bit
This should fix https://bugs.llvm.org//show_bug.cgi?id=34189

This change makes it so that if writing a K_GNU style archive, you need
to output a > 32-bit offset it should output in K_GNU64 style instead.

Differential Revision: https://reviews.llvm.org/D36812

llvm-svn: 316805
2017-10-27 22:26:37 +00:00
Krzysztof Parzyszek
a326e2735d [Hexagon] Adjust patterns to reflect instruction selection preferences
llvm-svn: 316804
2017-10-27 22:24:49 +00:00
David Blaikie
4faf7716f4 Add a few missing headers for modularization/IWYU/etc
Several cases where class definitions are required for DenseMap pointer
traits handling.

llvm-svn: 316803
2017-10-27 22:12:46 +00:00
Guozhi Wei
bb55a29e2c [DAGCombine] Don't combine sext with extload if sextload is not supported and extload has multi users
In function DAGCombiner::visitSIGN_EXTEND_INREG, sext can be combined with extload even if sextload is not supported by target, then

  if sext is the only user of extload, there is no big difference, no harm no benefit.
  if extload has more than one user, the combined sextload may block extload from combining with other zext, causes extra zext instructions generated. As demonstrated by the attached test case.

This patch add the constraint that when sextload is not supported by target, sext can only be combined with extload if it is the only user of extload.

Differential Revision: https://reviews.llvm.org/D39108

llvm-svn: 316802
2017-10-27 21:54:24 +00:00
Jake Ehrlich
c7b3bc6415 Make 32-bit member offset in Archive::Symbol::getMember 64-bit
When accessing a member for a symbol with an offset greater than 2^32 -
1 the current Archive::Symbol::getMember implementation will overflow
and cause unexpected behavior. This change simply fixes that. In
particular if you call "llvm-nm --print-armap" on an archive that has
this behavior you'll get an error.

Differential Revision: https://reviews.llvm.org/D39379

llvm-svn: 316801
2017-10-27 21:47:38 +00:00
Rafael Espindola
8302c0a6f3 Handle undefined weak hidden symbols on all architectures.
We were handling the non-hidden case in lib/Target/TargetMachine.cpp,
but the hidden case was handled in architecture dependent code and
only X86_64 and AArch64 were covered.

While it is true that some code sequences in some ABIs might be able
to produce the correct value at runtime, that doesn't seem to be the
common case.

I left the AArch64 code in place since it also forces a got access for
non-pic code. It is not clear if that is needed, but it is probably
better to change that in another commit.

llvm-svn: 316799
2017-10-27 21:18:48 +00:00
Zachary Turner
6c4fad5c56 Force #define GTEST_LANG_CXX11.
gtest depends on this #define to determine whether it can
use various classes like std::tuple, or whether it has to fall
back to experimental classes in the std::tr1 namespace.  The
check in the current version of gtest relies on the value of
the `__cplusplus` macro, but MSVC provides a non-conformant
value of this macro, making it effectively impossible to detect
C++11.  In short, LLVM compiled with MSVC has been silently
using the tr1 versions of several classes since the beginning of
time.

This would normally be pretty benign, except that in the latest
preview of MSVC they have marked all of the tr1 classes
deprecated, so it spews thousands of warnings.

llvm-svn: 316798
2017-10-27 21:12:28 +00:00
Craig Topper
84235f92a8 [X86] Remove fast-isel code for handling i8 shifts. This is handled by auto generated code.
llvm-svn: 316797
2017-10-27 21:00:59 +00:00
Craig Topper
a3b2a13a0d [X86] Add fast-isel tests for integer shifts. We definitely had no coverage of i16 and i32/i64 are only tested by larger tests.
llvm-svn: 316796
2017-10-27 21:00:56 +00:00
Artur Gainullin
74f6ea6c18 Improve clamp recognition in ValueTracking.
Summary:
ValueTracking was recognizing not all variations of clamp. Swapping of
true value and false value of select was added to fix this problem. The
first patch was reverted because it caused miscompile in NVPTX target. 
Added corresponding test cases.

Reviewers: spatel, majnemer, efriedma, reames

Subscribers: llvm-commits, jholewinski

Differential Revision: https://reviews.llvm.org/D39240

llvm-svn: 316795
2017-10-27 20:53:41 +00:00
Craig Topper
ff4b759e23 [X86] Teach fastisel to use VLX VMOVNTDQA for v4f64 and 256-bit integers when available.
This looks to have been missed from r280682.

llvm-svn: 316790
2017-10-27 20:13:10 +00:00
Craig Topper
4f1317a4b2 [X86] Add avx512vl command line to fast-isel-nontemporal.ll
llvm-svn: 316789
2017-10-27 20:13:06 +00:00
Vlad Tsyrklevich
c561d49cb8 Fix llvm-special-case-list-fuzzer regexp exception
Summary:
Original oss-fuzz report:
https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=3727#c2

The minimized test case that causes this failure:
5b 5b 5b 3d 47 53 00 5b  3d 5d 5b 5d 0a     [[[=GS.[=][].

Note the string "=GS\x00". The failure happens because the code is
searching the string against an array of known collated names. "GS\x00"
is a hit, but since len takes into account an extra NUL byte, indexing
into cp->name[len] goes one byte past it's allocated memory. Fix this to
use a strlen(cp->name) comparison to account for NUL bytes in the input.

Reviewers: pcc

Reviewed By: pcc

Subscribers: hctim, kcc

Differential Revision: https://reviews.llvm.org/D39380

llvm-svn: 316786
2017-10-27 19:15:13 +00:00
Krzysztof Parzyszek
ae1c4f0759 [Hexagon] Fix an incorrect assertion in HexagonConstExtenders.cpp
Making sure that an instruction has fewer operands than required, then
attempting to access one out of range is going to fail.

llvm-svn: 316785
2017-10-27 18:52:28 +00:00
Simon Pilgrim
2f122bccd5 [X86][SSE] Add tests for inserting all-bits (-1) into a vector
We should be able to do this by re-materializing an all-bits vector and then blending with it

llvm-svn: 316779
2017-10-27 18:14:12 +00:00
Peter Collingbourne
002558db01 ELF: Add support for emitting dynamic relocations in the Android relocation packing format.
The Android relocation packing format is a more compact
format for dynamic relocations in executables and DSOs
that is based on delta encoding and SLEBs. An overview
of the format can be found in the Android source code:
https://android.googlesource.com/platform/bionic/+/refs/heads/master/tools/relocation_packer/src/delta_encoder.h

This patch implements relocation packing using that format.

This implementation uses a more intelligent algorithm for compressing
relative relocations than Android's own relocation packer. As a
result it can generally create smaller relocation sections than
that packer. If I link Chromium for Android targeting ARM32 I get a
.rel.dyn of size 174693 bytes, as compared to 371832 bytes with gold
and the Android packer.

Differential Revision: https://reviews.llvm.org/D39152

llvm-svn: 316775
2017-10-27 17:49:40 +00:00
Simon Pilgrim
5fdbb3eb29 [X86][F16C] Fix btver2 AGU pipe scheduling
Use the store AGU for stores, and the load AGU needs to be the first pipe for loads

llvm-svn: 316771
2017-10-27 16:34:58 +00:00
Artur Pilipenko
4cfeec2c57 [LoopPredication] Handle the case when the guard and the latch IV have different offsets
This is a follow up change for D37569.

Currently the transformation is limited to the case when:
 * The loop has a single latch with the condition of the form: ++i <pred> latchLimit, where <pred> is u<, u<=, s<, or s<=.
 * The step of the IV used in the latch condition is 1.
 * The IV of the latch condition is the same as the post increment IV of the guard condition.
 * The guard condition is of the form i u< guardLimit.

This patch enables the transform in the case when the latch is

 latchStart + i <pred> latchLimit, where <pred> is u<, u<=, s<, or s<=.

And the guard is

 guardStart + i u< guardLimit

Reviewed By: anna

Differential Revision: https://reviews.llvm.org/D39097

llvm-svn: 316768
2017-10-27 14:46:17 +00:00
Clement Courbet
33872fb100 [CodeGen] Fix -Wunused-private-field warning on lld-x86_64-darwin13.
llvm-svn: 316765
2017-10-27 13:34:41 +00:00
Clement Courbet
159abef183 [CodeGen][ExpandMemCmp][NFC] Simplify load sequence generation.
llvm-svn: 316763
2017-10-27 12:34:18 +00:00
whitequark
198497f55f [LLVM-C] Publicly expose getters of MetadataType, TokenType
Patch by Robert Widmann.

Expose getters for MetadataType and TokenType publicly in the C API.
Discovered a need for these while trying to wrap the intrinsics API.

Differential Revision: https://reviews.llvm.org/D38809

llvm-svn: 316762
2017-10-27 11:51:40 +00:00
George Rimar
d6d8086a0f Fix BB after r316756 "[llvm-dwarfdump] - Teach verifier to report broken DWARF expressions."
Bot:
http://lab.llvm.org:8011/builders/clang-with-thin-lto-ubuntu/builds/6255

Changed format of this message by mistake.

llvm-svn: 316757
2017-10-27 10:58:04 +00:00
George Rimar
2e9ea7ed91 [llvm-dwarfdump] - Teach verifier to report broken DWARF expressions.
Patch improves next things:

* Fixes assert/crash in getOpDesc when giving it a invalid expression op code.
* DWARFExpression::print() called DWARFExpression::Operation::getEndOffset() which
  returned and used uninitialized field EndOffset. Patch fixes that.
* Teaches verifier to verify DW_AT_location and error out on broken expressions.

Differential revision: https://reviews.llvm.org/D39294

llvm-svn: 316756
2017-10-27 10:42:04 +00:00
Matt Arsenault
f9af63b514 DAG: Fold fma (fneg x), K, y -> fma x, -K, y
llvm-svn: 316753
2017-10-27 09:06:07 +00:00
Clement Courbet
89007bb7c7 [CodeGen][ExpandMemcmp][NFC] Make tests more complete.
llvm-svn: 316749
2017-10-27 08:33:51 +00:00
Max Kazantsev
5ec7323d94 [GVN][NFC] Refactor loop iteration with foreach
llvm-svn: 316748
2017-10-27 08:19:35 +00:00
NAKAMURA Takumi
af734a1671 llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h: Fix -fmodules build introduced in rL316715.
llvm-svn: 316743
2017-10-27 05:45:11 +00:00
Max Kazantsev
6d732d84e6 Revert rL316568 because of sudden performance drop on ARM
llvm-svn: 316739
2017-10-27 04:17:44 +00:00