Misha Brukman
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f2119a5b6f
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Separate instruction formats from instruction definitions.
llvm-svn: 15414
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2004-08-02 16:54:54 +00:00 |
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Misha Brukman
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148ad01de1
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Renamed files:
* PowerPCReg.td => PowerPCRegisterinfo.td
* PowerPCInstrs.td => PowerPCInstrInfo.td
llvm-svn: 15295
|
2004-07-27 23:29:16 +00:00 |
|
Misha Brukman
|
8c047d4fad
|
Add COND_BRANCH pseudo instruction, patch by Nate Begeman.
llvm-svn: 15283
|
2004-07-27 18:35:54 +00:00 |
|
Misha Brukman
|
93b0ea58a2
|
MovePCtoLR (which is `bl' in disguise) modifies LR implicitly
llvm-svn: 15272
|
2004-07-27 17:15:05 +00:00 |
|
Misha Brukman
|
3d395cbda3
|
Add SUBI instruction
llvm-svn: 15077
|
2004-07-21 15:53:04 +00:00 |
|
Misha Brukman
|
f47940855d
|
Differentiate between global and weak symbol loads
llvm-svn: 15037
|
2004-07-20 15:52:25 +00:00 |
|
Misha Brukman
|
f93e5532d5
|
Add IMPLICIT_DEFS pseudo-instruction; patch by: Nate Begeman
llvm-svn: 14895
|
2004-07-16 20:33:41 +00:00 |
|
Misha Brukman
|
efcb6b8c2c
|
* Coalesce the handy CALL* alias opcodes with the standard ones
* Congregate more branch-and-link opcodes together
* Mark FP, CPR, and special registers as volatile across calls
llvm-svn: 14511
|
2004-06-30 22:00:45 +00:00 |
|
Misha Brukman
|
2242e8d27f
|
* Use LA instead of LWZ for LoadLoAddr
* Specify the isCall bit and caller-save registers for some call instrs
llvm-svn: 14501
|
2004-06-29 23:37:36 +00:00 |
|
Misha Brukman
|
92cc94a0e5
|
Fix the assembly opcode on LOADLoAddr, courtesy of Nate Begeman.
llvm-svn: 14470
|
2004-06-28 18:27:08 +00:00 |
|
Misha Brukman
|
2f7332b752
|
Set isBranch and isTerminator bits on all branch instructions.
llvm-svn: 14469
|
2004-06-28 18:23:35 +00:00 |
|
Misha Brukman
|
269034c151
|
Initial revision
llvm-svn: 14283
|
2004-06-21 16:55:25 +00:00 |
|