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Commit Graph

108947 Commits

Author SHA1 Message Date
Daniel Dunbar
685b3765e0 Fix ShTest parsing error when a keyword line doesn't end with a newline.
llvm-svn: 220354
2014-10-22 00:34:31 +00:00
Matt Arsenault
c95fbccb3f Fix typo
llvm-svn: 220353
2014-10-22 00:28:59 +00:00
Matt Arsenault
66f5850df1 Try to fix documentation bot warning
llvm-svn: 220352
2014-10-22 00:15:53 +00:00
Evgeniy Stepanov
a0ac0578a6 [msan] Handle param-tls overflow.
ParamTLS (shadow for function arguments) is of limited size. This change
makes all arguments that do not fit unpoisoned, and avoids writing
past the end of a TLS buffer.

llvm-svn: 220351
2014-10-22 00:12:40 +00:00
Hans Wennborg
b55f26d3d1 Revert "Teach the load analysis to allow finding available values which require" (r220277)
This seems to have caused PR21330.

llvm-svn: 220349
2014-10-21 23:49:52 +00:00
Lang Hames
30fea694b9 [MCJIT] Defer application of AArch64 MachO GOT relocations until resolve time.
On AArch64, GOT references are page relative (ADRP + LDR), so they can't be
applied until we know exactly where, within a page, the GOT entry will be in
the target address space.

Fixes <rdar://problem/18693976>.

llvm-svn: 220347
2014-10-21 23:41:15 +00:00
Rafael Espindola
2cfc7cef2c MRI scripts: Add addlib support.
llvm-svn: 220346
2014-10-21 23:18:51 +00:00
JF Bastien
be14e0d9dd LTO: respect command-line options that disable vectorization.
Summary: Patches 202051 and 208013 added calls to LTO's PassManager which unconditionally add LoopVectorizePass and SLPVectorizerPass instead of following the logic in PassManagerBuilder::populateModulePassManager and honoring the -vectorize-loops -run-slp-after-loop-vectorization flags.

Reviewers: nadav, aschwaighofer, yijiang

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5884

llvm-svn: 220345
2014-10-21 23:18:21 +00:00
Rafael Espindola
57a9dbf097 Use a range loop. NFC.
llvm-svn: 220344
2014-10-21 23:04:55 +00:00
Matt Arsenault
2257f6b589 Add minnum / maxnum codegen
llvm-svn: 220342
2014-10-21 23:01:01 +00:00
Matt Arsenault
74dd906076 Add minnum / maxnum intrinsics
These are named following the IEEE-754 names for these
functions, rather than the libm fmin / fmax to avoid
possible ambiguities. Some languages may implement something
resembling fmin / fmax which return NaN if either operand is
to propagate errors. These implement the IEEE-754 semantics
of returning the other operand if either is a NaN representing
missing data.

llvm-svn: 220341
2014-10-21 23:00:20 +00:00
Duncan P. N. Exon Smith
38802ea9da IR: Reorder metadata bitcode serialization, NFC
Enumerate `MDNode`'s operands *before* the node itself, so that the
reader requires less RAUW.  Although this will cause different code
paths to be hit in the reader, this should effectively be no
functionality change.

llvm-svn: 220340
2014-10-21 22:27:47 +00:00
Matt Arsenault
98d33a4281 R600/SI: Add missing parameter to div_fmas intrinsic
llvm-svn: 220338
2014-10-21 22:20:55 +00:00
Duncan P. N. Exon Smith
ac50c13623 IR: Remove dead code in metadata bitcode writing, NFC
No one cares how many uses each metadata value has, so don't bother
counting.

llvm-svn: 220337
2014-10-21 22:13:34 +00:00
Rafael Espindola
c61ba0d3ae Overwrite instead of adding to archives when creating them in mri scripts.
This matches the behavior of GNU ar and also makes it easier to implemnt
support for the addlib command.

llvm-svn: 220336
2014-10-21 21:56:47 +00:00
Arnaud A. de Grandmaison
3555931ec7 Pacify bots and simplify r220321
llvm-svn: 220335
2014-10-21 21:50:49 +00:00
Rafael Espindola
aaaa7bf04a Convert a few std::string with StringRef. NFC.
This is a micro optimization, but also makes the code a bit more flexible.

The MRIMembers variable is a short term hack. It is going away in the next
commit.

llvm-svn: 220334
2014-10-21 21:47:27 +00:00
Reid Kleckner
e6f7feb7c7 GCC has supported C++11 ref-qualifiers since 4.8.1
This requires incorporating __GNUC_PATCHLEVEL__ into our prerequisite
check, and renaming our __GNUC_PREREQ to LLVM_GNUC_PREREQ, since it is
now functionally different.

Patch by Chilledheart!

Differential Revision: http://reviews.llvm.org/D5879

llvm-svn: 220332
2014-10-21 21:15:45 +00:00
Matt Arsenault
f60479b756 R600: Use default GlobalDirective
The overridden one wasn't inserting a space,
so you would end up with .globalfoo

llvm-svn: 220329
2014-10-21 21:08:36 +00:00
Rafael Espindola
a68d2115f3 Use a StringRef. No functionality change.
llvm-svn: 220327
2014-10-21 21:07:49 +00:00
Philip Reames
ee5103d817 Teach combineMetadata how to merge 'nonnull' metadata.
combineMetadata is used when merging two instructions into one.  This change teaches it how to merge 'nonnull' - i.e. only preserve it on the new instruction if it's set on both sources.  This isn't actually used yet since I haven't adjusted any of the call sites to pass in nonnull as a 'known metadata'.  

llvm-svn: 220325
2014-10-21 21:02:19 +00:00
Philip Reames
d832b51fdd Preserve 'nonnull' when changing type of the load.
When changing the type of a load in Chandler's recent InstCombine changes, we can preserve the new 'nonnull' metadata.  

I considered adding an assert since 'nonnull' is only valid on pointer types, but casting a pointer to a non-pointer would involve more than a bitcast anyways.  If someone extends this transform to handle more than bitcasts, the verifier will report the malformed IR, so a separate assertion isn't needed.  Also, the fpmath flags would have the same problem.

llvm-svn: 220324
2014-10-21 21:00:03 +00:00
Philip Reames
2458f7a6d1 Extend the verifier to check usage of 'nonnull' metadata.
The recently added !nonnull metadata is only valid on loads of pointer type.  

llvm-svn: 220323
2014-10-21 20:56:29 +00:00
Arnaud A. de Grandmaison
73624b6ac4 [PBQP] Teach PassConfig to tell if the default register allocator is used.
This enables targets to adapt their pass pipeline to the register
allocator in use. For example, with the AArch64 backend, using PBQP
with the cortex-a57, the FPLoadBalancing pass is no longer necessary.

llvm-svn: 220321
2014-10-21 20:47:22 +00:00
Rafael Espindola
05ca555aab Move code a bit to avoid a few declarations. NFC.
llvm-svn: 220317
2014-10-21 20:34:57 +00:00
Arnaud A. de Grandmaison
08bfa12a78 [PBQP] Add a testcase for r220302: Fix coalescing benefits
llvm-svn: 220316
2014-10-21 20:10:21 +00:00
David Majnemer
ebf53c54ae InstCombine: Simplify FoldICmpCstShrCst
This function was complicated by the fact that it tried to perform
canonicalizations that were already preformed by InstSimplify.  Remove
this extra code and move the tests over to InstSimplify.  Add asserts to
make sure our preconditions hold before we make any assumptions.

llvm-svn: 220314
2014-10-21 19:51:55 +00:00
Rafael Espindola
f1e8d6839e Drop support for an old version of ld64 (from darwin 9).
llvm-svn: 220310
2014-10-21 18:31:09 +00:00
Sanjay Patel
5ea6c4aa6e remove function names from comments; NFC
llvm-svn: 220309
2014-10-21 18:26:57 +00:00
Rafael Espindola
a453b6ac7a Convert two tests to use llvm-readobj.
llvm-svn: 220308
2014-10-21 18:24:31 +00:00
Matt Arsenault
bfd13cde1b R600/SI: Add pattern for bswap
llvm-svn: 220304
2014-10-21 16:25:08 +00:00
Arnaud A. de Grandmaison
75c3a6de21 [PBQP] Check for out of bound access in DEBUG builds
It is just too easy to use a virtual register intead of a NodeId without a
compiler warning. This does not fix the fundamental problem, i.e. both
have the same underlying types, but increases the likelyhood to detect it.

llvm-svn: 220303
2014-10-21 16:24:21 +00:00
Arnaud A. de Grandmaison
f39e772ae9 [PBQP] Fix coalescing benefits
As coalescing registers is a benefit, the cost should be improved (i.e. made smaller) when coalescing is possible.

llvm-svn: 220302
2014-10-21 16:24:15 +00:00
NAKAMURA Takumi
2ca8461092 X86AsmInstrumentation.cpp: Dissolve initializer-ranged-for. MSC17 disliked it.
llvm-svn: 220301
2014-10-21 16:22:52 +00:00
Aaron Ballman
be2dcb8639 Silence a -Wcast-qual warning; NFC.
llvm-svn: 220300
2014-10-21 16:12:37 +00:00
Colin LeMahieu
0a3ea08c1c Test commit
Fixing brief comment.

llvm-svn: 220299
2014-10-21 16:03:10 +00:00
Rafael Espindola
59c106d8c1 Comment cleanup. NFC.
Don't duplicate names in comments and remove useless ones. Hopefully anyone
reading this knows what main is.

llvm-svn: 220298
2014-10-21 15:49:46 +00:00
Rafael Espindola
134fc95edc Add support for addmod to mri scripts.
llvm-svn: 220294
2014-10-21 14:46:17 +00:00
Bill Schmidt
b654c2bb89 [PowerPC] Avoid VSX FMA mutate when killed product reg = addend reg
With VSX enabled, test/CodeGen/PowerPC/recipest.ll exposes a bug in
the FMA mutation pass.  If we have a situation where a killed product
register is the same register as the FMA target, such as:

   %vreg5<def,tied1> = XSNMSUBADP %vreg5<tied0>, %vreg11, %vreg5,
                       %RM<imp-use>; VSFRC:%vreg5 F8RC:%vreg11 

then the substitution makes no sense.  We end up getting a crash when
we try to extend the interval associated with the killed product
register, as there is already a live range for %vreg5 there.  This
patch just disables the mutation under those circumstances.

Since recipest.ll generates different code with VMX enabled, I've
modified that test to use -mattr=-vsx.  I've borrowed the code from
that test that exposed the bug and placed it in fma-mutate.ll, where
it tests several mutation opportunities including the "bad" one.

llvm-svn: 220290
2014-10-21 13:02:37 +00:00
Oliver Stannard
ecd544ccbd [ARM] NEON 32-bit scalar moves are also available in VFPv2
The 32-bit variants of the NEON scalar<->GPR move instructions are
also available in VFPv2. The 8- and 16-bit variants do require NEON.

Note that the checks in the test file are all -DAG because they are
checking a mixture of stdout and stderr, and the ordering is not
guaranteed.

llvm-svn: 220288
2014-10-21 11:49:14 +00:00
Yuri Gorshenin
a8f1a7e5da [asan-asm-instrumentation] Fixed memory accesses with rbp as a base or an index register.
Summary: Fixed memory accesses with rbp as a base or an index register.

Reviewers: eugenis

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D5819

llvm-svn: 220283
2014-10-21 10:22:27 +00:00
Oliver Stannard
70943b7fa8 [Thumb2] LDRS?[BH] cannot load to the PC
The Thumb2 LDRS?[BH] instructions are not valid when the destination
register is the PC (these encodings are used for preload hints).

llvm-svn: 220278
2014-10-21 09:14:15 +00:00
Chandler Carruth
eaa3d973ce Teach the load analysis to allow finding available values which require
inttoptr or ptrtoint cast provided there is datalayout available.
Eventually, the datalayout can just be required but in practice it will
always be there today.

To go with the ability to expose available values requiring a ptrtoint
or inttoptr cast, helpers are added to perform one of these three casts.

These smarts are necessary to finish canonicalizing loads and stores to
the operational type requirements without regressing fundamental
combines.

I've added some test cases. These should actually improve as the load
combining and store combining improves, but they may fundamentally be
highlighting some missing combines for select in addition to exercising
the specific added logic to load analysis.

llvm-svn: 220277
2014-10-21 09:00:40 +00:00
Zoran Jovanovic
5e356e74e3 [mips][microMIPS] Implement ADDU16 and SUBU16 instructions
Differential Revision: http://reviews.llvm.org/D5118

llvm-svn: 220276
2014-10-21 08:44:58 +00:00
Zoran Jovanovic
26b6fdd712 [mips][microMIPS] Implement AND16, NOT16, OR16 and XOR16 instructions
Differential Revision: http://reviews.llvm.org/D5117

llvm-svn: 220275
2014-10-21 08:32:40 +00:00
Zoran Jovanovic
7982f485af [mips][microMIPS] Implement microMIPS 16-bit instructions registers
Differential Revision: http://reviews.llvm.org/D5116

llvm-svn: 220273
2014-10-21 08:23:11 +00:00
Rafael Espindola
6ffbd5bf5d Fix a bit of confusion about .set and produce more readable assembly.
Every target we support has support for assembly that looks like

a = b - c
.long a

What is special about MachO is that the above combination suppresses the
production of a relocation.

With this change we avoid producing the intermediary labels when they don't
add any value.

llvm-svn: 220256
2014-10-21 01:17:30 +00:00
Paul Robinson
1e6411812d Do not attribute static allocas to the call site's DebugLoc.
When functions are inlined, instructions without debug information are
attributed to the call site's DebugLoc. After inlining, inlined static
allocas are moved to the caller's entry block, adjacent to the caller's
original static alloca instructions. By retaining the call site's
DebugLoc, these instructions could cause instructions that were
subsequently inserted at the entry block to pick up the same DebugLoc.

Patch by Wolfgang Pieb!

llvm-svn: 220255
2014-10-21 01:00:55 +00:00
Rafael Espindola
313a1829fa Make this test a bit more strict.
llvm-svn: 220253
2014-10-21 00:47:49 +00:00
Chandler Carruth
40ae319dfa Teach lit to filter the host LDFLAGS down from the build system and into
the CGO build environment. This lets things like -rpath propagate down
to the C++ code that is built along side the Go bindings when testing
them.

Patch by Peter Collingbourne, and verified that it works by me.

llvm-svn: 220252
2014-10-21 00:36:28 +00:00