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6 Commits

Author SHA1 Message Date
Vincent Lejeune
4a8c23c168 R600: Non vector only instruction can be scheduled on trans unit 
llvm-svn: 189980
 2013-09-04 19:53:46 +00:00
Tom Stellard
c6c9cd5b09 Revert "R600: Non vector only instruction can be scheduled on trans unit" 
This reverts commit 98ce62780ea7185ba710868bf83c8077e8d7f6d6.

llvm-svn: 187526
 2013-07-31 20:43:27 +00:00
Vincent Lejeune
2100f94811 R600: Non vector only instruction can be scheduled on trans unit 
llvm-svn: 187514
 2013-07-31 19:31:56 +00:00
Vincent Lejeune
62da1453e1 R600: Prettier asmPrint of Alu 
llvm-svn: 180956
 2013-05-02 21:52:30 +00:00
Benjamin Kramer
202c1b8357 Test case hygiene. 
llvm-svn: 176772
 2013-03-09 18:25:40 +00:00
Tom Stellard
6f17e7033b Add R600 backend 
A new backend supporting AMD GPUs: Radeon HD2XXX - HD7XXX

llvm-svn: 169915
 2012-12-11 21:25:42 +00:00