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Commit Graph

5243 Commits

Author SHA1 Message Date
Chad Rosier
69cdae5eb9 For immediate encodings of icmp, zero or sign extend first. Then
determine if the value is negative and flip the sign accordingly.
rdar://10422026

llvm-svn: 144258
2011-11-10 01:30:39 +00:00
Jakob Stoklund Olesen
bc48cd34b6 Strip old implicit operands after foldMemoryOperand.
The TII.foldMemoryOperand hook preserves implicit operands from the
original instruction.  This is not what we want when those implicit
operands refer to the register being spilled.

Implicit operands referring to other registers are preserved.

This fixes PR11347.

llvm-svn: 144247
2011-11-10 00:17:03 +00:00
Eli Friedman
c93f8aa514 Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.
llvm-svn: 144241
2011-11-09 23:36:02 +00:00
Eli Friedman
b01f15653c Add check so we don't try to perform an impossible transformation. Fixes issue from PR11319.
llvm-svn: 144216
2011-11-09 22:25:12 +00:00
Nadav Rotem
ddc6bfa543 AVX2: Add patterns for variable shift operations
llvm-svn: 144212
2011-11-09 21:22:13 +00:00
Chad Rosier
228dc76221 Use REs to remove dependencies on the register allocation order.
llvm-svn: 144209
2011-11-09 20:06:13 +00:00
Duncan Sands
2934a0eaeb Speculatively revert commit 144124 (djg) in the hope that the 32 bit
dragonegg self-host buildbot will recover (it is complaining about object
files differing between different build stages).  Original commit message:

Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.

llvm-svn: 144188
2011-11-09 14:20:48 +00:00
Nadav Rotem
e66a72a2c4 Add AVX2 support for vselect of v32i8
llvm-svn: 144187
2011-11-09 13:21:28 +00:00
Craig Topper
432dd8d623 Enable execution dependency fix pass for YMM registers when AVX2 is enabled. Add AVX2 logical operations to list of replaceable instructions.
llvm-svn: 144179
2011-11-09 09:37:21 +00:00
Craig Topper
7ff77dc2b1 Add instruction selection for AVX2 integer comparisons.
llvm-svn: 144176
2011-11-09 08:06:13 +00:00
Craig Topper
d82abb7156 Add AVX2 instruction lowering for add, sub, and mul.
llvm-svn: 144174
2011-11-09 07:28:55 +00:00
Chad Rosier
e32fed6868 Add support for encoding immediates in icmp and fcmp. Hopefully, this will
remove a fair number of unnecessary materialized constants.
rdar://10412592

llvm-svn: 144163
2011-11-09 03:22:02 +00:00
Jakob Stoklund Olesen
1239fed1e2 Collapse DomainValues across loop back-edges.
During the initial RPO traversal of the basic blocks, remember the ones
that are incomplete because of back-edges from predecessors that haven't
been visited yet.

After the initial RPO, revisit all those loop headers so the incoming
DomainValues on the back-edges can be properly collapsed.

This will properly fix execution domains on software pipelined code,
like the included test case.

llvm-svn: 144151
2011-11-09 01:06:56 +00:00
Dan Gohman
b6cf7c4e94 Add a hack to the scheduler to disable pseudo-two-address dependencies in
basic blocks containing calls. This works around a problem in which
these artificial dependencies can get tied up in calling seqeunce
scheduling in a way that makes the graph unschedulable with the current
approach of using artificial physical register dependencies for calling
sequences. This fixes PR11314.

llvm-svn: 144124
2011-11-08 21:29:06 +00:00
Evan Cheng
08e61752f2 Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ldm or ldr pairs.
llvm-svn: 144123
2011-11-08 21:21:09 +00:00
Pete Cooper
a1c151814a Adding test for machine-licm operating on invariant load instructions
llvm-svn: 144104
2011-11-08 19:06:53 +00:00
Lang Hames
ee7de1cff0 Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.
Add support for trimming constants to GetDemandedBits. This fixes some funky
constant generation that occurs when stores are expanded for targets that don't
support unaligned stores natively.

llvm-svn: 144102
2011-11-08 18:56:23 +00:00
NAKAMURA Takumi
e7c7964113 test/CodeGen/X86/vec_shuffle-39.ll: Add explicit -mtriple=x86_64-linux. Passing packed value is not compatible on Win32 x64.
llvm-svn: 144068
2011-11-08 03:46:39 +00:00
NAKAMURA Takumi
7094a0d830 test/CodeGen/X86/vec_shuffle-38.ll: Relax expression for Win32 x64.
llvm-svn: 144067
2011-11-08 03:46:32 +00:00
NAKAMURA Takumi
8bc13fe0b2 test/CodeGen/X86/vec_shuffle.ll: Add explicit -mtriple=i686-linux. We may see some suboptimal frame (%ebp) emission on certain hosts. Possible [PR11031]
llvm-svn: 144066
2011-11-08 03:46:25 +00:00
Eli Friedman
d5ba38a3d2 Make sure to mark vector extload's as expand on ARM. Fixes PR11319.
llvm-svn: 144057
2011-11-08 01:43:53 +00:00
Eli Friedman
741d364aa9 Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318.
Re-commit of r144034, with an extra fix so that RemoveDeadNode doesn't blow up.

llvm-svn: 144055
2011-11-08 01:25:24 +00:00
Evan Cheng
4a63100fe3 Add x86 isel logic and patterns to match movlps from clang generated IR for _mm_loadl_pi(). rdar://10134392, rdar://10050222
llvm-svn: 144052
2011-11-08 00:31:58 +00:00
Bill Wendling
788df1dca1 Convert to the new EH model.
llvm-svn: 144049
2011-11-08 00:17:28 +00:00
Bill Wendling
16499170c2 Convert tests to the new EH model.
llvm-svn: 144048
2011-11-08 00:09:27 +00:00
Chad Rosier
4b12a5b7fc Enable support for returning i1, i8, and i16. Nothing special todo as it's the
callee's responsibility to sign or zero-extend the return value.  The additional
test case just checks to make sure the calls are selected (i.e., -fast-isel-abort
doesn't assert).

llvm-svn: 144047
2011-11-08 00:03:32 +00:00
Pete Cooper
2f5c35ae89 Added missing newline
llvm-svn: 144046
2011-11-08 00:03:24 +00:00
Eli Friedman
8d138bf571 Revert r144034 while I try to track down a crash.
llvm-svn: 144044
2011-11-07 23:53:20 +00:00
Jakob Stoklund Olesen
1900a5f521 Fix test for Windows as well.
llvm-svn: 144038
2011-11-07 23:10:43 +00:00
Jakob Stoklund Olesen
9380d5daff Kill and collapse outstanding DomainValues.
DomainValues that are only used by "don't care" instructions are now
collapsed to the first possible execution domain after all basic blocks
have been processed.  This typically means the PS domain on x86.

For example, the vsel_i64 and vsel_double functions in sse2-blend.ll are
completely collapsed to the PS domain instead of containing a mix of
execution domains created by isel.

llvm-svn: 144037
2011-11-07 23:08:21 +00:00
Pete Cooper
1d5d364e06 InstCombine now optimizes vector udiv by power of 2 to shifts
Fixes r8429

llvm-svn: 144036
2011-11-07 23:04:49 +00:00
Eli Friedman
c1bb1b2b09 Add a bunch of calls to RemoveDeadNode in LegalizeDAG, so legalization doesn't get confused by CSE later on. Fixes PR11318.
llvm-svn: 144034
2011-11-07 22:51:10 +00:00
Benjamin Kramer
89ebc7ab4b Simplify some uses of utohexstr.
As a side effect hex is printed lowercase instead of uppercase now.

llvm-svn: 144013
2011-11-07 21:00:59 +00:00
Jakob Stoklund Olesen
d33a581d93 Fix test for Linux.
llvm-svn: 144003
2011-11-07 20:47:23 +00:00
Jakob Stoklund Olesen
b53be3a67d Expand V_SET0 to xorps by default.
The xorps instruction is smaller than pxor, so prefer that encoding.

The ExecutionDepsFix pass will switch the encoding to pxor and xorpd
when appropriate.

llvm-svn: 143996
2011-11-07 19:15:58 +00:00
Craig Topper
7eab73f510 Add AVX2 variable shift instructions and intrinsics.
llvm-svn: 143915
2011-11-07 08:26:24 +00:00
Craig Topper
b1ef950217 Add AVX2 VPMOVMASK instructions and intrinsics.
llvm-svn: 143904
2011-11-07 03:20:35 +00:00
Craig Topper
d422190c0f Add AVX2 VEXTRACTI128 and VINSERTI128 instructions. Fix VPERM2I128 to be qualified with HasAVX2 instead of HasAVX. Mark VINSERTF128 and VEXTRACTF128 as never having side effects.
llvm-svn: 143902
2011-11-07 02:00:04 +00:00
Craig Topper
01b852b95a More AVX2 instructions and their intrinsics.
llvm-svn: 143895
2011-11-06 23:04:08 +00:00
Craig Topper
31b1d79474 Add more AVX2 instructions and intrinsics.
llvm-svn: 143861
2011-11-06 06:12:20 +00:00
Chad Rosier
806ffd8918 Add support for passing i1, i8, and i16 call parameters. Also, be sure to
zero-extend the constant integer encoding.  Test case provides testing for
both call parameters and materialization of i1, i8, and i16 types.

llvm-svn: 143821
2011-11-05 20:16:15 +00:00
Benjamin Kramer
4c8932e3b8 Add an option to pad an uleb128 to MCObjectWriter and remove the uleb128 encoding from the DWARF asm printer.
As a side effect we now print dwarf ulebs with .ascii directives.

llvm-svn: 143809
2011-11-05 11:52:44 +00:00
Eli Friedman
1478b657c8 Enhanced vzeroupper insertion pass that avoids inserting vzeroupper where it is unnecessary through local analysis. Patch from Bruno Cardoso Lopes, with some additional changes.
I'm going to wait for any review comments and perform some additional testing before turning this on by default.

llvm-svn: 143750
2011-11-04 23:46:11 +00:00
Craig Topper
6ae8fe6fbe Add intrinsics for X86 vcvtps2ph and vcvtph2ps instructions
llvm-svn: 143682
2011-11-04 06:59:21 +00:00
Chad Rosier
21cd759234 Add fast-isel support for returning i1, i8, and i16.
llvm-svn: 143669
2011-11-04 00:50:21 +00:00
Dan Gohman
a5f382da8b Reapply r143206, with fixes. Disallow physical register lifetimes
across calls, and only check for nested dependences on the special
call-sequence-resource register.

llvm-svn: 143660
2011-11-03 21:49:52 +00:00
Pete Cooper
ad3d5b2eee Reverted r143600 - selector reference change
llvm-svn: 143646
2011-11-03 20:47:50 +00:00
Dan Bailey
986e6b02b8 fixed global array handling for ptx to use the correct bit widths
llvm-svn: 143640
2011-11-03 19:24:46 +00:00
Craig Topper
124b2fd08c Add new X86 AVX2 VBROADCAST instructions.
llvm-svn: 143612
2011-11-03 07:35:53 +00:00
Chad Rosier
74c4e2c2d9 Add support for sign-extending non-legal types in SelectSIToFP().
llvm-svn: 143603
2011-11-03 02:04:59 +00:00