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Commit Graph

128172 Commits

Author SHA1 Message Date
Craig Topper
29e5870acb [X86] Remove a couple returns after llvm_unreachables. NFC
llvm-svn: 261979
2016-02-26 05:29:39 +00:00
Craig Topper
f1c180e526 [X86] Use inclusive ranges for XMM/YMM/ZMM registers in is32Extended and isX86_64ExtendedReg. NFC
llvm-svn: 261978
2016-02-26 05:29:35 +00:00
Craig Topper
e52def5593 [X86] Explicitly diagnose use of %xmm16-%xmm31, %ymm16-%ymm31 and %zmm16-%zmm31 when AVX512 is not enabled in the asm parser.
llvm-svn: 261977
2016-02-26 05:29:32 +00:00
Hongbin Zheng
09e77e87cf Another fix the testcase introduced by r261903 - Add the missing matches
llvm-svn: 261971
2016-02-26 03:41:47 +00:00
Sanjoy Das
7fc83dcd6e Minor doc fix: statepoints are invokable too
llvm-svn: 261968
2016-02-26 03:33:59 +00:00
Matthias Braun
4033884b97 MachineCopyPropagation: Catch copies of the form A<-B;A<-B
Differential Revision: http://reviews.llvm.org/D17475

llvm-svn: 261966
2016-02-26 03:18:55 +00:00
Matthias Braun
7c163b2f7d MachineCopyPropagation: Keep scanning through instructions with regmasks
This also simplifies the code by removing the overly conservative
NoInterveningSideEffect() function. This function checked:
- That the two copies belong to the same block: We only process one
  block at a time and clear our maps in between it is impossible to find a
  copy from a different block.
- There is no terminator between the two copy instructions: This is not
  allowed anyway (the MachineVerifier would complain)
- Does not have instructions with hasUnmodeledSideEffects() or isCall()
  set: Even for those instructuction we must have all clobbers/defs of
  registers explicit as an operand. If the register is explicitely
  clobbered we would never come to the point of checking for
  NoInterveningSideEffect() anyway.

(I also checked this with a temporary build of the test-suite with all
 potentially failing conditions in NoInterveningSideEffect() turned into
 asserts)

Differential Revision: http://reviews.llvm.org/D17474

llvm-svn: 261965
2016-02-26 03:18:50 +00:00
Xinliang David Li
04309d54d1 [PGO] Add test case to ensure covmap section is not allocatable.
Differential Revision: http://reviews.llvm.org/D17324

llvm-svn: 261959
2016-02-26 03:05:10 +00:00
Michael Zolotukhin
4826fdb5cd [LoopUnrollAnalyzer] Check that we're using SCEV for the same loop we're simulating.
Summary: Check that we're using SCEV for the same loop we're simulating. Otherwise, we might try to use the iteration number of the current loop in SCEV expressions for inner/outer loops IVs, which is clearly incorrect.

Reviewers: chandlerc, hfinkel

Subscribers: sanjoy, llvm-commits, mzolotukhin

Differential Revision: http://reviews.llvm.org/D17632

llvm-svn: 261958
2016-02-26 02:57:05 +00:00
Junmo Park
527d68963a Minor code cleanups. NFC.
llvm-svn: 261955
2016-02-26 02:07:36 +00:00
Michael Zolotukhin
97ebaeb3fd [UnitTests] UnrollAnalyzer: make unit-test more general so that it can cover more cases in future.
llvm-svn: 261954
2016-02-26 01:44:04 +00:00
Mike Aizatsky
b65bb6da73 [sancov] Pruning full dominator blocks from instrumentation.
Summary:
This is the first simple attempt to reduce number of coverage-
instrumented blocks.

If a basic block dominates all its successors, then its coverage
information is useless to us. Ingore such blocks if
santizer-coverage-prune-tree option is set.

Differential Revision: http://reviews.llvm.org/D17626

llvm-svn: 261949
2016-02-26 01:17:22 +00:00
Sanjay Patel
944a9c8b96 [x86, SSE] add tests to show missing pcmp folds
llvm-svn: 261948
2016-02-26 01:14:27 +00:00
Xinliang David Li
0b2716e0f4 Add forward declarations /NFC
llvm-svn: 261946
2016-02-26 00:54:08 +00:00
David Majnemer
473ae5e981 [WinEH] Don't remove unannotated inline-asm calls
Inline-asm calls aren't annotated with funclet bundle operands because
they don't throw and cannot be inlined through.  We shouldn't require
them to bear an funclet bundle operand.

llvm-svn: 261942
2016-02-26 00:04:25 +00:00
Owen Anderson
d302ba20c3 More internal details of SROA pass to library visibility.
llvm-svn: 261934
2016-02-25 23:34:21 +00:00
Justin Bogner
da5fbf58c8 Support: Give ManagedStatic's helper object library visibility
It doesn't make much sense to export these symbols.

llvm-svn: 261931
2016-02-25 22:05:19 +00:00
Hemant Kulkarni
4d7cb7c1de Reverts change r261907 and r261918
llvm-svn: 261927
2016-02-25 20:47:07 +00:00
Hongbin Zheng
218c423299 Use regex in testcase, do not fail windows bots
llvm-svn: 261922
2016-02-25 19:16:40 +00:00
Hemant Kulkarni
afbfbdc65e Fix endianness issue on BE machines introduced by r261907
llvm-svn: 261918
2016-02-25 18:56:01 +00:00
David L Kreitzer
9eac7219b8 Reformatted a comment to fit the 80 column limit. NFC.
llvm-svn: 261916
2016-02-25 18:50:45 +00:00
Hongbin Zheng
33487f8384 Try to fix windows fail at r261902.
Introduce move constructor and move assignment operator to PostDominatorTree.

llvm-svn: 261910
2016-02-25 18:24:19 +00:00
Hemant Kulkarni
616aef8e81 [llvm-readobj] Enable GNU style sections and relocations printing
http://reviews.llvm.org/D17523

llvm-svn: 261907
2016-02-25 18:02:00 +00:00
Hongbin Zheng
f0c9856bf9 Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC
Differential Revision: http://reviews.llvm.org/D17571

llvm-svn: 261904
2016-02-25 17:54:25 +00:00
Hongbin Zheng
e391b241c7 Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC
Differential Revision: http://reviews.llvm.org/D17570

llvm-svn: 261903
2016-02-25 17:54:15 +00:00
Hongbin Zheng
3e75d3d4e5 Introduce analysis pass to compute PostDominators in the new pass manager. NFC
Differential Revision: http://reviews.llvm.org/D17537

llvm-svn: 261902
2016-02-25 17:54:07 +00:00
Tim Northover
50249c2bb2 ARM: disallow pc as a base register in Thumb2 memory ops.
These should all be deferring to the "OP (literal)" variant according to the
ARM ARM.

llvm-svn: 261895
2016-02-25 16:54:52 +00:00
Hongbin Zheng
3d17e7bc47 Revert "Introduce analysis pass to compute PostDominators in the new pass manager. NFC"
This reverts commit a3e5cc6a51ab5ad88d1760c63284294a4e34c018.

llvm-svn: 261891
2016-02-25 16:45:53 +00:00
Hongbin Zheng
b446bc1e4f Revert "Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC"
This reverts commit 109c38b2226a87b0be73fa7a0a8c1a81df20aeb2.

llvm-svn: 261890
2016-02-25 16:45:46 +00:00
Hongbin Zheng
4f423eca95 Revert "Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC"
This reverts commit 8228b4d374edeb4cc0c5fddf6e1ab876918ee126.

llvm-svn: 261889
2016-02-25 16:45:37 +00:00
Sanjay Patel
699293f9ca rangify; NFCI
llvm-svn: 261888
2016-02-25 16:44:27 +00:00
Geoff Berry
ef03e5a8d3 [AArch64] Clean up callee-save CFI emission. NFC.
Summary:
Avoid special case for FP, LR CFI emission and just allow general
AArch64FrameLowering::emitCalleeSavedFrameMoves() to handle them.  Also,
stop recalculating the stack offsets in emitCalleeSavedFrameMoves()
since we can just reuse the previously calculated offset stored in the
MachineFrameInfo.

Depends on D17000

Reviewers: t.p.northover, rengolin, mcrosier, jmolloy

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D17004

llvm-svn: 261885
2016-02-25 16:36:08 +00:00
Hongbin Zheng
4a56a70d94 Introduce RegionInfoAnalysis, which compute Region Tree in the new PassManager. NFC
Differential Revision: http://reviews.llvm.org/D17571

llvm-svn: 261884
2016-02-25 16:33:26 +00:00
Hongbin Zheng
10a5a19fa0 Introduce DominanceFrontierAnalysis to the new PassManager to compute DominanceFrontier. NFC
Differential Revision: http://reviews.llvm.org/D17570

llvm-svn: 261883
2016-02-25 16:33:15 +00:00
Hongbin Zheng
26e597b0c3 Introduce analysis pass to compute PostDominators in the new pass manager. NFC
Differential Revision: http://reviews.llvm.org/D17537

llvm-svn: 261882
2016-02-25 16:33:06 +00:00
Nikolay Haustov
b57a0b698b [AMDGPU] Disassembler: Support for all VOP1 instructions.
Support all instructions with VOP1 encoding with 32 or 64-bit operands for VI subtarget:

VGPR_32 and VReg_64 operand register classes
VS_32 and VS_64 operand register classes with inline and literal constants
Tests for VOP1 instructions.

Patch by: skolton

Reviewers: arsenm, tstellarAMD

Review: http://reviews.llvm.org/D17194
llvm-svn: 261878
2016-02-25 16:09:14 +00:00
Sanjay Patel
4ad8d0c9b8 don't repeat names in documentation comments; NFC
llvm-svn: 261877
2016-02-25 15:55:28 +00:00
Igor Breger
c2763588ac AVX512F: Add GATHER/SCATTER assembler Intel syntax tests for knl/skx/avx . Change memory operand parser handling.
Differential Revision: http://reviews.llvm.org/D17564

llvm-svn: 261862
2016-02-25 13:30:17 +00:00
Hrvoje Varga
a7d72fcec9 [mips][microMIPS] Implement DINSU, DINSM, DINS instructions
Differential Revision: http://reviews.llvm.org/D16181

llvm-svn: 261860
2016-02-25 12:53:29 +00:00
Nikolay Haustov
f6baecf637 [AMDGPU] Assembler: Simplify handling of optional operands
Resubmit with index problem fixed. Verified with valgrind.

Prepare to support DPP encodings.

For DPP encodings, we want row_mask/bank_mask/bound_ctrl to be optional operands.
However this means that when parsing instruction which has no mnemonic prefix,
we cannot add both default values for VOP3 and for DPP optional operands
to OperandVector - neither instructions would match. So add default values
for optional operands to MCInst during conversion instead.

Mark more operands as IsOptional = 1 in .td files.
Do not add default values for optional operands to OperandVector in AMDGPUAsmParser.
Add default values for optional operands during conversion using new helper addOptionalImmOperand.
Change to cvtVOP3_2_mod to check instruction flag instead of presence of modifiers. In the future, cvtVOP3* functions can be combined into one.
Separate cvtFlat and cvtFlatAtomic.
Fix CNDMASK_B32 definition to have no modifiers.

Review: http://reviews.llvm.org/D17445
llvm-svn: 261856
2016-02-25 10:58:54 +00:00
Chandler Carruth
8e1f184ecc [PM] Add the IR unit type to the pass manager's logging and make all of
the testing more more explicit.

This will currently fail on platforms without support for getTypeName.
While an assert failure seems too harsh, I'm hoping we're OK with the
regression test failure, and I'd like to find out about what platforms
actually exist in this state if there are any so we can get
implementations in place for them.

But if we just can't fix all the host compilers to have a reasonably
portable variant of getTypeName and are worried about xfailing this test
on those platforms, I can add the horrible regular expression magic to
make the tests support "unknown" here as well.

llvm-svn: 261853
2016-02-25 10:27:39 +00:00
Simon Pilgrim
67f60b197d [X86][SSE3] Added combine support for MOVDDUP/MOVSHDUP/MOVSLDUP target shuffles
Now that PerformShuffleCombine can handle unary shuffles.

llvm-svn: 261843
2016-02-25 09:12:12 +00:00
NAKAMURA Takumi
26ceb67a9c Revert r260064, "Disable llvm/test/tools/llvm-profdata/value-prof.proftext on win32 for now. Investigating."
It seems unreproducible any more for me.

llvm-svn: 261842
2016-02-25 08:50:26 +00:00
NAKAMURA Takumi
71379d5304 Revert r261742, "[AMDGPU] Assembler: Simplify handling of optional operands"
It brought undefined behavior.

llvm-svn: 261839
2016-02-25 08:35:27 +00:00
Justin Bogner
5af532d89d PM: Implement a basic loop pass manager
This creates the new-style LoopPassManager and wires it up with dummy
and print passes.

This version doesn't support modifying the loop nest at all. It will
be far easier to discuss and evaluate the approaches to that with this
in place so that the boilerplate is out of the way.

llvm-svn: 261831
2016-02-25 07:23:08 +00:00
Elena Demikhovsky
b3f8b2cb2e Optimized loading (zextload) of i1 value from memory.
This patch is a partial revert of https://llvm.org/svn/llvm-project/llvm/trunk@237793.
Extra "and" causes performance degradation.

We assume that i1 is stored in zero-extended form. And store operation is responsible for zeroing upper bits.

Differential Revision: http://reviews.llvm.org/D17541

llvm-svn: 261828
2016-02-25 07:05:12 +00:00
Chandler Carruth
39c2a60170 [Support] Don't check for ICC directly and rely on the __GNUC__ check
(which they emulate). This way we don't use that path when compiled with
ICC on Windows where it mimics MSVC's behavior and supports __FUNCSIG__.

Thanks for David Majnemer again for spotting this better pattern!

llvm-svn: 261827
2016-02-25 06:13:01 +00:00
Chandler Carruth
1895f07cd4 [Support] Add a fancy helper function to get a static name for a type.
This extracts the type name from __PRETTY_FUNCTION__ for compilers that
support it (I've opted Clang, GCC, and ICC into this as I've tested that
they work) and from __FUNCSIG__ which is very similar on MSVC. The
routine falls back gracefully on a stub "UNKNOWN_TYPE" string with
compilers or formats it doesn't understand.

This should be enough for a lot of common cases in LLVM where the real
goal is just to log or print a type name as a debugging aid, and save
a ton of boilerplate in the process. Notably, I'm planning to use this
to remove all the getName() boiler plate from the new pass manager.

The design and implementation is based on a bunch of advice and
discussion with Richard Smith and experimenting with most versions of
Clang and GCC. David Majnemer also provided excellent advice on how best
to do this with MSVC. Richard also checked that ICC does something
reasonable and I'll watch the build bots for other compilers. It'd be
great if someone could contribute logic for xlC and/or other toolchains.

Differential Revision: http://reviews.llvm.org/D17565

llvm-svn: 261819
2016-02-25 03:58:21 +00:00
Justin Bogner
24f8ffc3c6 IR: Make the X / undef -> undef fold match the comment
The constant folding for sdiv and udiv has a big discrepancy between the
comments and the code, which looks like a typo. Currently, we're folding
X / undef pretty inconsistently:

  0 / undef -> undef
  C / undef -> 0
  undef / undef -> 0

Whereas the comments state we do X / undef -> undef. The logic that
returns zero is actually commented as doing undef / X -> 0, despite that
the LHS isn't undef in many of the cases that hit it.

llvm-svn: 261813
2016-02-25 01:02:18 +00:00
Junmo Park
e684ff35db [CodeGenPrepare] Remove load-based heuristic
Summary:
Both the hardware and LLVM have changed since 2012.
Now, load-based heuristic don't show big differences any more on OoO cores.

There is no notable regressons and improvements on spec2000/2006. (Cortex-A57, Core i5).

Reviewers: spatel, zansari
    
Differential Revision: http://reviews.llvm.org/D16836

llvm-svn: 261809
2016-02-25 00:23:27 +00:00