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Commit Graph

57782 Commits

Author SHA1 Message Date
Jakub Staszak
6a77423b5f Remove unneeded function, since PR8156 was fixed over a year ago.
llvm-svn: 169534
2012-12-06 19:05:46 +00:00
Jakub Staszak
b18925a384 Simplify code.
llvm-svn: 169521
2012-12-06 18:22:59 +00:00
Nadav Rotem
5b43aa0b29 Fix a bug in the code that merges consecutive stores. Previously we did not
check if loads that happen in between stores alias with the first store in the
chain, only with the second store onwards.

llvm-svn: 169516
2012-12-06 17:34:13 +00:00
NAKAMURA Takumi
8847f19308 MemorySanitizer.cpp: Suppress a warning. [-Wunused-variable]
llvm-svn: 169504
2012-12-06 13:38:00 +00:00
Evgeniy Stepanov
1ad21b4153 [msan] Fix a typo in a comment.
llvm-svn: 169491
2012-12-06 11:58:59 +00:00
Evgeniy Stepanov
97d6933f46 [msan] Do not store origin for clean values.
Instead of unconditionally storing origin with every application store,
only do this when the shadow of the stored value is != 0.

This change also delays instrumentation of stores until after the walk over
function's instructions, because adding new basic blocks confuses InstVisitor.

We only keep 1 origin value per 4 bytes of application memory. This change
fixes the bug when a store of a single clean byte wiped the origin for the
whole 4-byte area.

Since stores of uninitialized values are relatively uncommon, this change
improves performance of track-origins mode by 5% median and by up to 47% on
specs.

llvm-svn: 169490
2012-12-06 11:41:03 +00:00
Bill Wendling
9cb80ecabb s/getLowerBoundDefault/getDefaultLowerBound/ for consistency. Also put the more natural check first in the if-then statement.
llvm-svn: 169486
2012-12-06 07:55:19 +00:00
Bill Wendling
979b24c6ec Handle non-default array bounds.
Some languages, e.g. Ada and Pascal, allow you to specify that the array bounds
are different from the default (1 in these cases). If we have a lower bound
that's non-default, then we emit the lower bound. We also calculate the correct
upper bound in those cases.

llvm-svn: 169484
2012-12-06 07:38:10 +00:00
Craig Topper
e907c5dd53 Remove intrinsic specific instructions for (V)MOVQUmr with patterns pointing to the normal instructions.
llvm-svn: 169482
2012-12-06 07:31:16 +00:00
Craig Topper
32786c4c50 Mark MOVDQ(A/U)rm as ReMaterializable. Mark all MOVDQ(A/U) instructions as neverHasSideEffects.
llvm-svn: 169477
2012-12-06 06:49:16 +00:00
NAKAMURA Takumi
79cb136d31 Revert r169456, "change MCContext to work on the doInitialization/doFinalization model"
It broke many builders.

llvm-svn: 169462
2012-12-06 02:00:13 +00:00
Chad Rosier
c7e4217273 [arm fast-isel] Make the fast-isel implementation of memcpy respect alignment.
rdar://12821569

llvm-svn: 169460
2012-12-06 01:34:31 +00:00
Evan Cheng
c1db873871 Let targets provide hooks that compute known zero and ones for any_extend
and extload's. If they are implemented as zero-extend, or implicitly
zero-extend, then this can enable more demanded bits optimizations. e.g.

define void @foo(i16* %ptr, i32 %a) nounwind {
entry:
  %tmp1 = icmp ult i32 %a, 100
  br i1 %tmp1, label %bb1, label %bb2
bb1:
  %tmp2 = load i16* %ptr, align 2
  br label %bb2
bb2:
  %tmp3 = phi i16 [ 0, %entry ], [ %tmp2, %bb1 ]
  %cmp = icmp ult i16 %tmp3, 24
  br i1 %cmp, label %bb3, label %exit
bb3:
  call void @bar() nounwind
  br label %exit
exit:
  ret void
}

This compiles to the followings before:
        push    {lr}
        mov     r2, #0
        cmp     r1, #99
        bhi     LBB0_2
@ BB#1:                                 @ %bb1
        ldrh    r2, [r0]
LBB0_2:                                 @ %bb2
        uxth    r0, r2
        cmp     r0, #23
        bhi     LBB0_4
@ BB#3:                                 @ %bb3
        bl      _bar
LBB0_4:                                 @ %exit
        pop     {lr}
        bx      lr

The uxth is not needed since ldrh implicitly zero-extend the high bits. With
this change it's eliminated.

rdar://12771555

llvm-svn: 169459
2012-12-06 01:28:01 +00:00
Pedro Artigas
e62d631d01 change MCContext to work on the doInitialization/doFinalization model
reviewed by Evan Cheng <evan.cheng@apple.com>

llvm-svn: 169456
2012-12-06 00:50:55 +00:00
Bill Wendling
7119fab4de Set the 'MadeChange' variable if we are deleting blocks.
llvm-svn: 169455
2012-12-06 00:30:20 +00:00
Michael Ilseman
bd2183badf Have CannotBeNegativeZero() be aware of the nsz fast-math flag
llvm-svn: 169452
2012-12-06 00:07:09 +00:00
Andrew Trick
1a2b4ddd59 RegPressureTracker::dump(): Remove unnecessary argument.
llvm-svn: 169443
2012-12-05 23:05:22 +00:00
Eli Bendersky
7b68fe1bd8 Change std::vector to SmallVector<4> and remove some unused methods.
This is more consistent with other vectors in this code. In addition, I ran some
tests compiling a large program and >96% of fragments have 4 or less fixups, so
SmallVector<4> is a good optimization.

llvm-svn: 169433
2012-12-05 22:11:02 +00:00
Jyotsna Verma
9995a62d05 Define new-value store instructions with base+immediate addressing mode
using multiclass.

llvm-svn: 169432
2012-12-05 22:02:56 +00:00
Bill Wendling
826cff4dbc Fix name. The array is unboundED.
llvm-svn: 169428
2012-12-05 21:43:30 +00:00
Andrew Trick
69c3ea61f2 RegisterPressureTracker: fix findUseBetween to handle DebugValue
llvm-svn: 169427
2012-12-05 21:37:50 +00:00
Andrew Trick
4360a22194 RegisterPressureTracker: unify virtual registers and physical regunits.
Now that live register units are tracked individually, the code can be simplified.

llvm-svn: 169426
2012-12-05 21:37:47 +00:00
Andrew Trick
67c084b14c RegisterPresssureTracker: Track live physical register by unit.
This is much simpler to reason about, more efficient, and
fixes some corner cases involving implicit super-register defs.
Fixed rdar://12797931.

llvm-svn: 169425
2012-12-05 21:37:42 +00:00
Nadav Rotem
6dac3b0c66 Cost Model: change the default cost of control flow instructions (br / ret / ...) to zero.
llvm-svn: 169423
2012-12-05 21:21:26 +00:00
David Sehr
f67cd34524 Correct ARM NOP encoding
The encoding of NOP in ARMAsmBackend.cpp is missing a trailing zero, which
causes the emission of a coprocessor instruction rather than "mov r0, r0"
as indicated in the comment.  The test also checks for the wrong encoding.

http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20121203/157919.html

llvm-svn: 169420
2012-12-05 21:01:27 +00:00
Justin Holewinski
22f8d09057 [NVPTX] Fix crash with unnamed struct arguments
Patch by Eric Holk

llvm-svn: 169418
2012-12-05 20:50:28 +00:00
Jyotsna Verma
c8d145f6f6 Use multiclass to define store instructions with base+immediate offset
addressing mode and immediate stored value.

llvm-svn: 169408
2012-12-05 19:32:03 +00:00
Bob Wilson
29106bfeff Adjust JIT target triple on OS X to match the current architecture.
For OS X builds, we generate one version of config.h but then build for
multiple architectures.  This means that the LLVM_HOSTTRIPLE setting may have
the wrong architecture.  Adjust it dynamically to match the current
architecture.  <rdar://problem/12715470>

llvm-svn: 169405
2012-12-05 19:09:13 +00:00
Matthew Curtis
67b48517cb Fix misplaced closing brace.
llvm-svn: 169404
2012-12-05 19:00:34 +00:00
Benjamin Kramer
e66030212a Try to unbreak the build on hosts that don't transitively pull in a definition for int64_t.
Also use the portable (ugly) format string macros, for MSVC compatibility.

llvm-svn: 169396
2012-12-05 18:31:11 +00:00
Jakob Stoklund Olesen
75ccdbb1dc Remove unused MachineInstr constructors.
A MachineInstr can only ever be constructed by CreateMachineInstr() and
CloneMachineInstr(), and those factories don't use the removed
constructors.

llvm-svn: 169395
2012-12-05 18:27:39 +00:00
Kevin Enderby
94941df94f Added a option to the disassembler to print immediates as hex.
This is for the lldb team so most of but not all of the values are
to be printed as hex with this option.  Some small values like the
scale in an X86 address were requested to printed in decimal
without the leading 0x.

There may be some tweaks need to places that may still be in
decimal that they want in hex.  Specially for arm.  I made my best
guess.  Any tweaks from here should be simple.

I also did the best I know now with help from the C++ gurus
creating the cleanest formatImm() utility function and containing
the changes.  But if someone has a better idea to make something
cleaner I'm all ears and game for changing the implementation.

rdar://8109283

llvm-svn: 169393
2012-12-05 18:13:19 +00:00
Pedro Artigas
cd715362f7 - Added calls to doInitialization/doFinalization to immutable passes
- fixed ordering of calls to doFinalization to be the reverse of the pass run order due to potential dependencies
- fixed machine module info to operate in the doInitialization/doFinalization model, also fixes some FIXMEs

reviewed by Evan Cheng <evan.cheng@apple.com>

llvm-svn: 169391
2012-12-05 17:12:22 +00:00
Evgeniy Stepanov
21dc8412a5 [msan] Instrument bswap intrinsic.
llvm-svn: 169383
2012-12-05 14:39:55 +00:00
Evgeniy Stepanov
06e754c093 [msan] Initialize callbacks in runOnFunction as opposed to doInitialization.
This mirrors the change in ASan & TSan done in r168864.

llvm-svn: 169378
2012-12-05 13:14:33 +00:00
Evgeniy Stepanov
597a835dbc [msan] Change linkage type of __msan_track_origins.
LinkOnceODRLinkage globals may be removed in GlobalOpt if not used in the
current module.

llvm-svn: 169377
2012-12-05 12:49:41 +00:00
Elena Demikhovsky
fa1ab36215 Simplified BLEND pattern matching for shuffles.
Generate VPBLENDD for AVX2 and VPBLENDW for v16i16 type on AVX2.

llvm-svn: 169366
2012-12-05 09:24:57 +00:00
Andrew Trick
7da96db06b Added RegisterPressureTracker::dump() for debugging.
llvm-svn: 169359
2012-12-05 06:47:08 +00:00
Michael J. Spencer
c0bd8f95ce Copy clang/Driver/<Option parsing stuff> to llvm.
llvm-svn: 169344
2012-12-05 00:29:32 +00:00
Evan Cheng
f87900c4b1 Add x86 isel lowering logic to form bit test with inverted condition. e.g.
x ^ -1.

Patch by David Majnemer.
rdar://12755626

llvm-svn: 169339
2012-12-05 00:10:38 +00:00
Matt Beaumont-Gay
fd804eb89d Appease GCC's -Wparentheses.
(TIL that Clang's -Wparentheses ignores 'x || y && "foo"' on purpose. Neat.)

llvm-svn: 169337
2012-12-04 23:54:02 +00:00
Bill Wendling
e6735aeca0 Split up the ParseOptionalAttrs method into three different methods for each
class of attributes. This makes it much easier to check for errors and to reuse
the code.

llvm-svn: 169336
2012-12-04 23:40:58 +00:00
Nadav Rotem
4990f6a07b LoopVectorizer: Increase the number of pointers that can be tested at runtime. If we cant prove statically that the pointers are disjoint then we add the runtime check.
llvm-svn: 169334
2012-12-04 23:25:24 +00:00
Nadav Rotem
c58f94b665 Enable if-conversion during vectorization.
llvm-svn: 169331
2012-12-04 22:59:52 +00:00
Evan Cheng
cae5a79f6b ARM custom lower ctpop for vector types. Patch by Pete Couperus.
llvm-svn: 169325
2012-12-04 22:41:50 +00:00
Nadav Rotem
452993ad1a Fix a bug in vectorization of if-converted reduction variables. If the
reduction variable is not used outside the loop then we ran into an
endless loop. This change checks if we found the original PHI.

llvm-svn: 169324
2012-12-04 22:40:22 +00:00
Jakob Stoklund Olesen
2db1b3c4ac Speed up the AllocationOrder class a bit.
Allow the central functions to be inlined, and use the argumentless
isHint() function when possible.

llvm-svn: 169319
2012-12-04 22:25:16 +00:00
Shuxin Yang
c390be6a5d For rdar://12329730, last piece.
This change attempts to simplify (X^Y) -> X or Y in the user's context if we know that
only bits from X or Y are demanded.

  A minimized case is provided bellow. This change will simplify "t>>16" into "var1 >>16".

  =============================================================
  unsigned foo (unsigned val1, unsigned val2) {
    unsigned t = val1 ^ 1234;
    return (t >> 16) | t; // NOTE: t is used more than once.
  }
  =============================================================

  Note that if the "t" were used only once, the expression would be finally optimized as well.
However, with with this change, the optimization will take place earlier.

  Reviewed by Nadav, Thanks a lot!

llvm-svn: 169317
2012-12-04 22:15:32 +00:00
David Blaikie
b56f347902 Comment change made in r169304 as requested by Eric Christopher.
llvm-svn: 169315
2012-12-04 22:02:33 +00:00
Jyotsna Verma
52d66f1d1e Define store instructions with base+register offset addressing mode
using multiclass.

llvm-svn: 169314
2012-12-04 21:58:25 +00:00