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Commit Graph

191853 Commits

Author SHA1 Message Date
LLVM GN Syncbot
6a9205d7eb [gn build] Port 49bffa5f8b7 2020-02-13 20:43:19 +00:00
serge-sans-paille
2f80dd8494 Fix handling of --version in lit
There's no reason why we should require a directory when asking for the version.

Differential Revision: https://reviews.llvm.org/D74553
2020-02-13 21:36:12 +01:00
Matt Arsenault
03c0cac41f AMDGPU/GlobalISel: Make G_TRUNC legal
This is required to be legal. I'm not sure how we were getting away
without defining any rules for it.
2020-02-13 15:25:52 -05:00
Matt Arsenault
8f4091003d GlobalISel: Don't use LLT references
These should always be passed by value
2020-02-13 15:25:30 -05:00
Frederic Bastien
8f84b444b1 [NVPTX, LSV] Move the LSV optimization pass to later when the graph is cleaner
This allow it to recognize more loads as being consecutive when the load's address are complex at the start.

Differential Revision: https://reviews.llvm.org/D74444
2020-02-13 12:15:38 -08:00
Vedant Kumar
1cb48ac1e6 Revert "Recommit "[SCCP] Remove forcedconstant, go to overdefined instead""
This reverts commit bb310b3f73dde5551bc2a0d564e88f7c831dfdb3. This
breaks the stage2 ASan build, see:

https://bugs.llvm.org/show_bug.cgi?id=44898

rdar://59431448
2020-02-13 11:55:18 -08:00
Greg Clayton
32dd03dc63 Fix buildbots that create shared libraries from GSYM library by adding a dependency on LLVMDebugInfoDWARF. 2020-02-13 11:43:07 -08:00
Greg Clayton
e962ea1e6c Fix buildbots by not using "and" and "not". 2020-02-13 11:35:43 -08:00
Ted Woodward
c26064a116 Clean up hexagon builder after object-emission removal
Original commit:
https://reviews.llvm.org/rG7683a084de6bd2637f2351f53389df8b610566cf
2020-02-13 13:17:42 -06:00
LLVM GN Syncbot
015b913f76 [gn build] Port 19602b71949 2020-02-13 18:52:48 +00:00
Greg Clayton
ccea019faf Add a DWARF transformer class that converts DWARF to GSYM.
Summary:
The DWARF transformer is added as a class so it can be unit tested fully.

The DWARF is converted to GSYM format and handles many special cases for functions:
- omit functions in compile units with 4 byte addresses whose address is UINT32_MAX (dead stripped)
- omit functions in compile units with 8 byte addresses whose address is UINT64_MAX (dead stripped)
- omit any functions whose high PC is <= low PC (dead stripped)
- StringTable builder doesn't copy strings, so we need to make backing copies of strings but only when needed. Many strings come from sections in object files and won't need to have backing copies, but some do.
- When a function doesn't have a mangled name, store the fully qualified name by creating a string by traversing the parent decl context DIEs and then. If we don't do this, we end up having cases where some function might appear in the GSYM as "erase" instead of "std::vector<int>::erase".
- omit any functions whose address isn't in the optional TextRanges member variable of DwarfTransformer. This allows object file to register address ranges that are known valid code ranges and can help omit functions that should have been dead stripped, but just had their low PC values set to zero. In this case we have many functions that all appear at address zero and can omit these functions by making sure they fall into good address ranges on the object file. Many compilers do this when the DWARF has a DW_AT_low_pc with a DW_FORM_addr, and a DW_AT_high_pc with a DW_FORM_data4 as the offset from the low PC. In this case the linker can't write the same address to both the high and low PC since there is only a relocation for the DW_AT_low_pc, so many linkers tend to just zero it out.

Reviewers: aprantl, dblaikie, probinson

Subscribers: mgorny, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74450
2020-02-13 10:48:37 -08:00
Matt Arsenault
857c9207d4 AMDGPU/GlobalISel: Add missing tests for cmpxchg selection 2020-02-13 10:26:55 -08:00
Yuanfang Chen
dd53274771 Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes.

Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on
MachineVerifierPass by default on X86 and the fact that
inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll
are not expected to generate functioning machine code, this would go
down to `report_fatal_error` in MachineVerifierPass. Here passing
`-verify-machineinstrs=0` to make the intent explicit.
2020-02-13 10:16:06 -08:00
Yuanfang Chen
2dbac841f9 Revert "Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit""""
This reverts commit bb51d243308dbcc9a8c73180ae7b9e47b98e68fb.
2020-02-13 10:08:05 -08:00
Yuanfang Chen
93e82c22ef Revert "Revert "Reland "[Support] make report_fatal_error abort instead of exit"""
This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes.

On bots llvm-clang-x86_64-expensive-checks-ubuntu and
llvm-clang-x86_64-expensive-checks-debian only,
llc returns 0 for these two tests unexpectedly. I tweaked the RUN line a little
bit in the hope that LIT is the culprit since this change is not in the
codepath these tests are testing.
llvm\test\CodeGen\X86\inline-asm-avx-v-constraint-32bit.ll
llvm\test\CodeGen\X86\inline-asm-avx512vl-v-constraint-32bit.ll
2020-02-13 10:02:53 -08:00
Nikita Popov
99acf1bd20 [MemorySSA] Don't verify MemorySSA unless VerifyMemorySSA enabled
MemorySSA is often taking up an unreasonable fraction of runtime in
assertion enabled builds. Turns out that there is one code-path that
runs verifyMemorySSA() even if VerifyMemorySSA is not enabled. This
patch makes it conditional as well.

Differential Revision: https://reviews.llvm.org/D74505
2020-02-13 18:46:58 +01:00
Matt Arsenault
f95863ff55 AMDGPU: Use v_perm_b32 to implement bswap
Also greatly improve i64 lowering. LegalizeIntegerTypes does the
correct narrowing if i64 isn't legal. Just workaround this for
SelectionDAG by making i64 legal and splitting in the patterns.
2020-02-13 09:45:31 -08:00
John Brawn
ad62d2e7de [ARM] Fix infinite loop when lowering STRICT_FP_EXTEND
If the target has FP64 but not FP16 then we have custom lowering for FP_EXTEND
and STRICT_FP_EXTEND with type f64. However if the extend is from f32 to f64 the
current implementation will cause in infinite loop for STRICT_FP_EXTEND due to
emitting a merge_values of the original node which after replacement becomes a
merge_values of itself.

Fix this by not doing anything for f32 to f64 extend when we have FP64, though
for STRICT_FP_EXTEND we have to do the strict-to-nonstrict mutation as that
doesn't happen automatically for opcodes with custom lowering.

Differential Revision: https://reviews.llvm.org/D74559
2020-02-13 16:12:50 +00:00
Sanjay Patel
946d17fa5b [VectorCombine] adjust tests for extract-binop; NFC
We want the extra-use tests to be consistent with the
earlier single-use tests and be as cheap as possible
in vector form to show cost model edge cases. So use
i8 and extract from element 0 since that should be
cheap for all x86 targets.
2020-02-13 10:51:01 -05:00
Sanjay Patel
7dfed75fcc [VectorCombine] add more extract-binop tests; NFC
See D74495.
2020-02-13 10:07:20 -05:00
Francesco Petrogalli
0612ebecbb [llvm][lldb] Update links to ABI for the Arm Architecture. [NFC] 2020-02-13 14:57:53 +00:00
Sean Fertile
0d0a2b6d3c [PowerPC][NFC] Small cleanup to restore CR field code in PPCFrameLowering.
Skip the loop over the CalleSavedInfos in 'restoreCalleeSavedRegisters' when
the register is a CR field and we are not targeting 32-bit ELF. This is safe
because:
1) The helper function 'restoreCRs' returns if the target is not 32-bit ELF,
   making all the code in the loop related to CR fields dead for every other
   subtarget. This code is only called on ELF right now, but the patch
   to extend it for AIX also needs to skip 'restoreCRs'.
2) The loop will not otherwise modify the iterator, so the iterator
   manipulations at the bottom of the loop end up setting 'I' to its
   current value.

This simplifciation allows us to remove one argument from 'restoreCRs'.

Also add a helper function to determine if a register is one of the
callee saved condition register fields.
2020-02-13 09:50:28 -05:00
Simon Pilgrim
d851cf8ef2 Move FIXME to start of comment so visual studio actually tags it. NFC. 2020-02-13 14:28:50 +00:00
Simon Pilgrim
ea74bfe847 [X86][SSE] Add i686-SSE2 bswap vector tests 2020-02-13 14:28:49 +00:00
Nico Weber
10c7916487 [gn build] Fix sync script on renames like "Foo.cpp" -> "LLVMFoo.cpp"
Before, the script used `git log -SFoo.cpp` to find a commit where
the number of occurrences of "Foo.cpp" changed -- but since
a patch with

  + LLVMFoo.cpp
  - Foo.cpp

contains the same number of instances of "Foo.cpp", the script
incorrectly skipped this type of rename.

As fix, look for '\bFoo\.cpp\b' instead and pass --pickaxe-regex
so that we can grep for word boundaries.

To test, check out 7531a5039fd (which renamed in llvm/lib/IR
RemarkStreamer.cpp to LLVMRemarkStreamer.cpp) and look at the output of
the script.  Before this change, it correctly assigned the addition
of LLVMRemarkStreamer.cpp to 7531a5039fd but incorrectly assigned
the removal of RemarkStreamer.cpp to b8a847c.  With this, it
correctly assigns both to 7531a5039fd.
2020-02-13 09:26:47 -05:00
serge-sans-paille
dd5b542685 Fix integration of pass plugins with llvm dylib
Call llvm_process_pass_plugin from clang when in standalone mode.

Differential Revision: https://reviews.llvm.org/D74464
2020-02-13 14:18:08 +01:00
serge-sans-paille
eff8b15a75 Rework go bindings so that validation works fine
Basically change the layout to please `go build` and remove references to
`llvm-go`.

Update llvm/test/Bindings/Go/ to use the system go compiler

Differential Revision: https://reviews.llvm.org/D74540
2020-02-13 14:13:03 +01:00
Qiu Chaofan
a735dedfe5 [PowerPC] Exploit VSX rounding instrs for rint
Exploit native VSX rounding instruction, x(v|s)r(d|s)pic, which does
rounding using current rounding mode.

According to C standard library, rint may raise INEXACT exception while
nearbyint won't.

Reviewed By: lkail

Differential Revision: https://reviews.llvm.org/D72685
2020-02-13 20:59:50 +08:00
stozer
b6fc689526 Re-revert: Recover debug intrinsics when killing duplicated/empty blocks
This reverts commit 61b35e4111160fe834a00c33d040e01150b576ac.

This commit causes a timeout in chromium builds; likely to have a
similar cause to the previous timeout issue caused by this commit (see
6ded69f294a9 for more details). It is possible that there is no way to
fix this bug that will not cause this issue; further investigations as
to the efficiency of handling large amounts of debug info will be
necessary.
2020-02-13 11:48:19 +00:00
Daniel Kiss
245ebfa635 [AArch64] Fix BTI landing pad generation.
In some cases BTI landing pad is inserted even compatible instruction
was there already. Meta instruction does not count in this case
therefore skip them in the check for first instructions in the function.

Differential revision: https://reviews.llvm.org/D74492
2020-02-13 10:44:34 +00:00
Kerry McLaughlin
b7041a91bb [AArch64][SVE] Add mul/mla/mls lane & dup intrinsics
Summary:
Implements the following intrinsics:
 - @llvm.aarch64.sve.dup
 - @llvm.aarch64.sve.mul.lane
 - @llvm.aarch64.sve.mla.lane
 - @llvm.aarch64.sve.mls.lane

Reviewers: c-rhodes, sdesmalen, dancgr, efriedma, rengolin

Reviewed By: sdesmalen

Subscribers: tschuett, kristof.beyls, hiraditya, rkruppe, psnobl, cfe-commits, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74222
2020-02-13 10:32:59 +00:00
David Green
61eab1d530 [ARM] Fix ReconstructShuffle for bigendian
Simon pointed out that this function is doing a bitcast, which can be
incorrect for big endian. That makes the lowering of VMOVN in MVE
wrong, but the function is shared between Neon and MVE so both can
be incorrect.

This attempts to fix things by using the newly added VECTOR_REG_CAST
instead of the BITCAST. As it may now be used on Neon, I've added the
relevant patterns for it there too. I've also added a quick dag combine
for it to remove them where possible.

Differential Revision: https://reviews.llvm.org/D74485
2020-02-13 09:56:46 +00:00
David Green
aa89daf1c2 [ARM] Extra vmovn tests to show BE differences. NFC 2020-02-13 09:56:46 +00:00
Roman Lebedev
01b56f3a2c [NFC][llvm-exegesis] Docs/help: opcode-index=-1 means measure everything 2020-02-13 12:46:12 +03:00
Igor Kudrin
2da0ac3ddb [DebugInfo] Fix dumping CIE ID in .eh_frame sections.
We do not keep the actual value of the CIE ID field, because it is
predefined, and use a constant when dumping a CIE record. The issue
was that the predefined value is different for .debug_frame and
.eh_frame sections, but we always printed the one which corresponds
to .debug_frame. The patch fixes that by choosing an appropriate
constant to print.

See the following for more information about .eh_frame sections:
https://refspecs.linuxfoundation.org/LSB_5.0.0/LSB-Core-generic/LSB-Core-generic/ehframechpt.html

Differential Revision: https://reviews.llvm.org/D73627
2020-02-13 15:42:14 +07:00
Johannes Doerfert
a084e15b3b [OpenMP][FIX] Collect blocks to be outlined after finalization
Finalization can introduce new blocks we need to outline as well so it
makes sense to identify the blocks that need to be outlined after
finalization happened. There was also a minor unit test adjustment to
account for the fact that we have a single outlined exit block now.
2020-02-13 00:42:22 -06:00
Vladimir Vereschaka
4bc72f1985 Revert "Replace std::foo with std::foo_t in LLVM."
This reverts commit a4384c756bd8a819051009b5b273b2a34be8261b.

These changes break LLVM build on Windows builders.

See https://reviews.llvm.org/rGa4384c756bd8a819051009b5b273b2a34be8261b
for details.
2020-02-12 20:54:21 -08:00
Craig Topper
752053399d [X86] Add test RUN lines to show cases where we use 512-bit vcmppd/ps with garbage upper bits for 128/256-bit strict_fsetcc
On KNL targets, we widen 128/256-bit strict_fsetcc nodes to
512-bits without forcing the upper bits to zero. This can cause
spurious exceptions due to garbage upper bits. This behavior was
inherited from the non-strict case where the spurious exception
isn't a problem.
2020-02-12 20:51:52 -08:00
Yonghong Song
cf18c2c0f8 [BPF] explicit warning of not supporting dynamic stack allocation
Currently, BPF does not support dynamic static allocation.
For a program like below:
  extern void bar(int *);
  void foo(int n) {
    int a[n];
    bar(a);
  }

The current error message looks like:
  unimplemented operand
  UNREACHABLE executed at /.../llvm/lib/Target/BPF/BPFISelLowering.cpp:199!

Let us make error message explicit so it will be clear to the user
what is the problem. With this patch, the error message looks like:
  fatal error: error in backend: Unsupported dynamic stack allocation
  ...

Differential Revision: https://reviews.llvm.org/D74521
2020-02-12 20:43:06 -08:00
Johannes Doerfert
17f538d282 Reapply "[OpenMP][IRBuilder] Perform finalization (incl. outlining) late"
Reapply 8a56d64d7620b3764f10f03f3a1e307fcdd72c2f with minor fixes.

The problem was that cancellation can cause new edges to the parallel
region exit block which is not outlined. The CodeExtractor will encode
the information which "exit" was taken as a return value. The fix is to
ensure we do not return any value from the outlined function, to prevent
control to value conversion we ensure a single exit block for the
outlined region.

This reverts commit 3aac953afa34885a72df96f2b703b65f85cbb149.
2020-02-12 22:29:07 -06:00
Serguei Katkov
ca1a0c2e8f [Statepoint] Remove redundant clear of call target on register
Patchable statepoint is lowered into sequence of nops, so zeroed call target
should not be on register. It is better to use getTargetConstant instead
of getConstant to select zero constant for call target.

Reviewers: reames
Reviewed By: reames
Subscribers: llvm-commits
Differential Revision: https://reviews.llvm.org/D74465
2020-02-13 10:25:50 +07:00
Austin Kerbow
305dffc7b7 [AMDGPU][GlobalISel] Handle 64byte EltSIze in getRegSplitParts
Reviewers: arsenm

Subscribers: kzhuravl, jvesely, wdng, nhaehnle, yaxunl, rovka, dstuttard, tpr, t-tye, hiraditya, llvm-commits

Tags: #llvm

Differential Revision: https://reviews.llvm.org/D74518
2020-02-12 19:11:52 -08:00
Nico Weber
7332bd4dc7 Fix ReST syntax on link to "Bisecting LLVM code" page
Patch from nicolas17 (Nicolás Alvarez)!

Differential Revision: https://reviews.llvm.org/D74422
2020-02-12 21:18:25 -05:00
Fangrui Song
a9c1f8f10e [AsmPrinter][ELF] Emit local alias for ExternalLinkage dso_local GlobalAlias 2020-02-12 17:08:22 -08:00
Amy Huang
3f8a544115 Revert "[X86][SSE] lowerShuffleAsBitRotate - lower to vXi8 shuffles to ROTL on pre-SSSE3 targets"
This reverts commit 11c16e71598d51f15b4cfd0f719c4dabcc0bebf7 because it
causes a crash in chromium code. See
https://reviews.llvm.org/rG11c16e71598d51f15b4cfd0f719c4dabcc0bebf7.
2020-02-12 17:00:37 -08:00
Johannes Doerfert
b34872013b Revert "[OpenMP][IRBuilder] Perform finalization (incl. outlining) late"
This reverts commit 8a56d64d7620b3764f10f03f3a1e307fcdd72c2f.

Will be recommitted once the clang test problem is addressed.
2020-02-12 18:50:43 -06:00
Matt Arsenault
6fdf8e6b26 AMDGPU/GlobalISel: Select G_CTTZ_ZERO_UNDEF
Directly select this rather than going through the intermediate
instruction, which may provide some combine value in the future.
2020-02-12 16:19:46 -08:00
Matt Arsenault
3eb9775837 AMDGPU/GlobalISel: Select G_CTLZ_ZERO_UNDEF
Directly select this rather than going through the intermediate
instruction, which may provide some combine value in the future.
2020-02-12 16:19:45 -08:00
Matt Arsenault
ab1b814c33 AMDGPU/GlobalISel: Fix mapping G_ICMP with constrained result
When SI_IF is inserted, it constrains the source register with a
register class, which was quite likely a G_ICMP. This was incorrectly
treating it as a scalar, and then applyMappingImpl would end up
producing invalid MIR since this was unexpected.

Also fix not using all VGPR sources for vcc outputs.
2020-02-12 16:19:45 -08:00
Matt Arsenault
3a9f8d3df6 PPC: Prepare tests for switch of default denormal-fp-math
These tests fail when the default is switched to assume IEEE denormal
handling. I'm not sure if PPC really has a way to control the denormal
input handling.
2020-02-12 16:19:45 -08:00