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1336 Commits

Author SHA1 Message Date
Evan Cheng
6b7d127df9 getPostIndexedAddressParts change: passes in load/store instead of its loaded / stored VT. 
llvm-svn: 31584
 2006-11-09 04:29:46 +00:00
Evan Cheng
fcef896f6e Match more post-indexed ops. 
llvm-svn: 31569
 2006-11-08 20:27:27 +00:00
Jim Laskey
28fec74f1b Remove redundant <cmath>. 
llvm-svn: 31561
 2006-11-08 19:16:44 +00:00
Evan Cheng
1f5c4a6c43 - When performing pre-/post- indexed load/store transformation, do not worry 
about whether the new base ptr would be live below the load/store. Let two
  address pass split it back to non-indexed ops.
- Minor tweaks / fixes.

llvm-svn: 31544
 2006-11-08 08:30:28 +00:00
Evan Cheng
acc6a98286 Fixed a minor bug preventing some pre-indexed load / store transformation. 
llvm-svn: 31543
 2006-11-08 06:56:05 +00:00
Reid Spencer
da1f5b882a For PR950: 
This patch converts the old SHR instruction into two instructions,
AShr (Arithmetic) and LShr (Logical). The Shr instructions now are not
dependent on the sign of their operands.

llvm-svn: 31542
 2006-11-08 06:47:33 +00:00
Evan Cheng
e50f5e4c05 Fix a obscure post-indexed load / store dag combine bug. 
llvm-svn: 31537
 2006-11-08 02:38:55 +00:00
Evan Cheng
3db2b3aab9 Add post-indexed load / store transformations. 
llvm-svn: 31498
 2006-11-07 09:03:05 +00:00
Chris Lattner
c8d5fc4461 Fix PR988 and CodeGen/Generic/2006-11-06-MemIntrinsicExpand.ll. 
The low part goes in the first operand of expandop, not the second one.

llvm-svn: 31487
 2006-11-07 04:11:44 +00:00
Evan Cheng
ef1c22b6fa Remove dead code; added a missing null ptr check. 
llvm-svn: 31478
 2006-11-06 21:33:46 +00:00
Evan Cheng
f191d53a9a Add comment. 
llvm-svn: 31473
 2006-11-06 08:14:30 +00:00
Jeff Cohen
e1003da1a2 Unbreak VC++ build. 
llvm-svn: 31464
 2006-11-05 19:31:28 +00:00
Evan Cheng
bf7db95159 Added pre-indexed store support. 
llvm-svn: 31459
 2006-11-05 09:31:14 +00:00
Evan Cheng
ae357e5044 Added getIndexedStore. 
llvm-svn: 31458
 2006-11-05 09:30:09 +00:00
Evan Cheng
42cb1fd0ac Changes to use operand constraints to process two-address instructions. 
llvm-svn: 31453
 2006-11-04 09:44:31 +00:00
Evan Cheng
047a33d3e3 Fix comments. 
llvm-svn: 31414
 2006-11-03 07:31:32 +00:00
Evan Cheng
466e20fca2 Rename 
llvm-svn: 31413
 2006-11-03 07:21:16 +00:00
Reid Spencer
8cac48e619 Remove dead variable. Fix 80 column violations. 
llvm-svn: 31412
 2006-11-03 03:30:34 +00:00
Evan Cheng
a0133317f7 Added DAG combiner transformation to generate pre-indexed loads. 
llvm-svn: 31410
 2006-11-03 03:06:21 +00:00
Evan Cheng
b9ed18642c Added isPredecessor. 
llvm-svn: 31409
 2006-11-03 03:05:24 +00:00
Chris Lattner
d4881b4e2d silence warning 
llvm-svn: 31397
 2006-11-03 01:28:29 +00:00
Reid Spencer
4bafa71dc1 For PR786: 
Turn on -Wunused and -Wno-unused-parameter. Clean up most of the resulting
fall out by removing unused variables. Remaining warnings have to do with
unused functions (I didn't want to delete code without review) and unused
variables in generated code. Maintainers should clean up the remaining
issues when they see them. All changes pass DejaGnu tests and Olden.

llvm-svn: 31380
 2006-11-02 20:25:50 +00:00
Reid Spencer
1abf69e923 For PR950: 
Replace the REM instruction with UREM, SREM and FREM.

llvm-svn: 31369
 2006-11-02 01:53:59 +00:00
Chris Lattner
35cd439221 Allow the getRegForInlineAsmConstraint method to return a register class with 
no fixes physreg.  Treat this as permission to use any register in the register
class.  When this happens and it is safe, allow the llvm register allcoator to
allocate the register instead of doing it at isel time.  This eliminates a ton
of copies around common inline asms.  For example:

int test2(int Y, int X) {
  asm("foo %0, %1" : "=r"(X): "r"(X));
  return X;
}

now compiles to:

_test2:
        foo r3, r4
        blr

instead of:

_test2:
        mr r2, r4
        foo r2, r2
        mr r3, r2
        blr

GCC produces:

_test2:
        foo r4, r4
        mr r3,r4
        blr

llvm-svn: 31366
 2006-11-02 01:41:49 +00:00
Evan Cheng
1f18eca4f5 Clean up. 
llvm-svn: 31359
 2006-11-01 22:39:30 +00:00
Evan Cheng
5479bb9fc4 CopyFromReg starts a live range so its use should not be considered a floater. 
llvm-svn: 31356
 2006-11-01 22:17:06 +00:00
Evan Cheng
67c04b1f2a Print jumptable index. 
llvm-svn: 31340
 2006-11-01 04:48:30 +00:00
Chris Lattner
850ef9955d Compile CodeGen/PowerPC/fp-branch.ll to: 
_intcoord_cond_next55:
LBB1_3: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        blt cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
        li r3, 1
        blr
LBB1_2: ;cond_next62.exitStub
        li r3, 0
        blr

instead of:

_intcoord_cond_next55:
LBB1_3: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        bge cr0, LBB1_1 ;bb72.exitStub
LBB1_4: ;cond_next55
        lis r2, ha16(LCPI1_0)
        lfs f0, lo16(LCPI1_0)(r2)
        fcmpu cr0, f1, f0
        bnu cr0, LBB1_2 ;cond_next62.exitStub
LBB1_1: ;bb72.exitStub
        li r3, 1
        blr
LBB1_2: ;cond_next62.exitStub
        li r3, 0
        blr

llvm-svn: 31330
 2006-10-31 23:06:00 +00:00
Chris Lattner
3131b7d6d1 look through isunordered to inline it into branch blocks. 
llvm-svn: 31328
 2006-10-31 22:37:42 +00:00
Chris Lattner
3bc1ad2c4a handle global address constant sdnodes 
llvm-svn: 31323
 2006-10-31 20:01:56 +00:00
Chris Lattner
a44a27dc47 TargetLowering::isOperandValidForConstraint 
llvm-svn: 31319
 2006-10-31 19:41:18 +00:00
Chris Lattner
d9afd310a6 Change the prototype for TargetLowering::isOperandValidForConstraint 
llvm-svn: 31318
 2006-10-31 19:40:43 +00:00
Chris Lattner
a9f10b25cc Turn an assert into an error message. This is commonly triggered when 
we don't support a specific constraint yet.  When this happens, print the
unsupported constraint.

llvm-svn: 31310
 2006-10-31 07:33:13 +00:00
Evan Cheng
3da8d26445 Fix a typo which can break jumptables. 
llvm-svn: 31305
 2006-10-31 02:31:00 +00:00
Evan Cheng
972f469722 Lower jumptable to BR_JT. The legalizer can lower it to a BRIND or let the target custom lower it. 
llvm-svn: 31293
 2006-10-30 08:00:44 +00:00
Evan Cheng
7437ed9f30 Added a new SDNode type: BR_JT for jumptable branch. 
llvm-svn: 31292
 2006-10-30 07:59:36 +00:00
Chris Lattner
46a439780e fix Generic/2006-10-29-Crash.ll 
llvm-svn: 31281
 2006-10-29 21:01:20 +00:00
Chris Lattner
0a5d859ae3 Fix a load folding issue that Evan noticed: there is no need to export values 
used by comparisons in the main block.

llvm-svn: 31279
 2006-10-29 18:23:37 +00:00
Evan Cheng
fa1756d048 VLOAD is not the LoadSDNode opcode. 
llvm-svn: 31276
 2006-10-29 06:14:47 +00:00
Nick Lewycky
baef048f71 Remove spurious case. EXTLOAD is not one of the node opcodes. 
llvm-svn: 31275
 2006-10-29 02:26:30 +00:00
Chris Lattner
776740f897 split critical edges more carefully and intelligently. In particular, critical 
edges whose destinations are not phi nodes don't bother us.  Also, share
split edges, since the split edge can't have a phi.  This significantly
reduces the complexity of generated code in some cases.

llvm-svn: 31274
 2006-10-28 19:22:10 +00:00
Jim Laskey
26ac9ac4ad Load and stores have not been uniqued properly. 
llvm-svn: 31261
 2006-10-28 17:25:28 +00:00
Chris Lattner
ee8a70f370 Split *all* critical edges before isel. This resolves issues with spill code 
being inserted on unsplit critical edges, which introduces (sometimes large
amounts of) partially dead spill code.

This also fixes PR925 + CodeGen/Generic/switch-crit-edge-constant.ll

llvm-svn: 31260
 2006-10-28 17:04:37 +00:00
Chris Lattner
f44a34d817 Fix a serious bug that caused any x86 vector stuff to infinite loop 
llvm-svn: 31254
 2006-10-28 06:15:26 +00:00
Jim Laskey
17bfaab377 Clean up. 
llvm-svn: 31243
 2006-10-27 23:52:51 +00:00
Chris Lattner
e009249ae1 Fix a bug in merged condition handling (CodeGen/Generic/2006-10-27-CondFolding.ll). 
Add many fewer CFG edges and PHI node entries.  If there is a switch which has
the same block as multiple destinations, only add that block once as a successor/phi
node (in the jumptable case)

llvm-svn: 31242
 2006-10-27 23:50:33 +00:00
Jim Laskey
ef56bc9680 Switch over from SelectionNodeCSEMap to FoldingSet. 
llvm-svn: 31240
 2006-10-27 23:46:08 +00:00
Chris Lattner
e2297cd5a6 remove debug code 
llvm-svn: 31233
 2006-10-27 21:58:03 +00:00
Chris Lattner
0fab97080c Codegen cond&cond with two branches. This compiles (f.e.) PowerPC/and-branch.ll to: 
cmpwi cr0, r4, 4
        bgt cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_3: ;entry
        cmplwi cr0, r3, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r3, r4, r3
        rlwinm r2, r2, 30, 31, 31
        or r2, r2, r3
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock
LBB1_1: ;cond_true

llvm-svn: 31232
 2006-10-27 21:54:23 +00:00
Chris Lattner
05159debc4 Turn conditions like x<Y|z==q into multiple blocks. 
This compiles Regression/CodeGen/X86/or-branch.ll into:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $5, %eax
        jl LBB1_1       #cond_true
LBB1_3: #entry
        testl %ecx, %ecx
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

instead of:

_foo:
        subl $12, %esp
        call L_bar$stub
        movl 20(%esp), %eax
        movl 16(%esp), %ecx
        cmpl $4, %eax
        setg %al
        testl %ecx, %ecx
        setne %cl
        testb %cl, %al
        jne LBB1_2      #UnifiedReturnBlock
LBB1_1: #cond_true
        call L_bar$stub
        addl $12, %esp
        ret
LBB1_2: #UnifiedReturnBlock
        addl $12, %esp
        ret

And on ppc to:

        cmpwi cr0, r29, 5
        blt cr0, LBB1_1 ;cond_true
LBB1_3: ;entry
        cmplwi cr0, r30, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

instead of:

        cmpwi cr7, r4, 4
        mfcr r2
        addic r4, r3, -1
        subfe r30, r4, r3
        rlwinm r29, r2, 30, 31, 31
        and r2, r29, r30
        cmplwi cr0, r2, 0
        bne cr0, LBB1_2 ;UnifiedReturnBlock

llvm-svn: 31230
 2006-10-27 21:36:01 +00:00