Joey Gouly
7f15046246
[ARM] Remove an unused function from the disassembler.
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Pointed out by Joerg.
llvm-svn: 191749
2013-10-01 13:01:10 +00:00
Matheus Almeida
7a5f5ed788
Test commit. Updated comment.
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llvm-svn: 191748
2013-10-01 12:53:00 +00:00
Richard Sandiford
ac3360b004
[SystemZ] Add register zero extensions involving at least one high word
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llvm-svn: 191746
2013-10-01 12:49:07 +00:00
Joey Gouly
12afb60cf2
[ARM] Introduce the 'sevl' instruction in ARMv8.
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This also removes the restriction on the immediate field of the 'hint'
instruction.
llvm-svn: 191744
2013-10-01 12:39:11 +00:00
Richard Sandiford
192be1070b
[SystemZ] Add truncating high-word stores (STCH and STHH)
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llvm-svn: 191743
2013-10-01 12:22:49 +00:00
Richard Sandiford
de433bf58d
[SystemZ] Add zero-extending high-word loads (LLCH and LLHH)
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llvm-svn: 191742
2013-10-01 12:19:08 +00:00
Benjamin Kramer
e04c4c3faf
SCEVExpander: Fix a regression I introduced by to eagerly adding RAII objects.
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PR17425.
llvm-svn: 191741
2013-10-01 12:17:11 +00:00
Richard Sandiford
dd8ae7a617
[SystemZ] Add sign-extending high-word loads (LBH and LHH)
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llvm-svn: 191740
2013-10-01 12:11:47 +00:00
Richard Sandiford
c2e496f7ba
[SystemZ] Use upper words of GR64s for codegen
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This just adds the basics necessary for allocating the upper words to
virtual registers (move, load and store). The move support is parameterised
in a way that makes it easy to handle zero extensions, but the associated
zero-extend patterns are added by a later patch.
The easiest way of testing this seemed to be add a new "h" register
constraint for high words. I don't expect the constraint to be useful
in real inline asms, but it should work, so I didn't try to hide it
behind an option.
llvm-svn: 191739
2013-10-01 11:26:28 +00:00
Richard Sandiford
21933530e5
[SystemZ] Reapply: Add definitions of LFH and STFH
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Originally committed as r191661, but reverted because it changed the matching
order of comparisons on some hosts. That should have been fixed by r191735.
llvm-svn: 191738
2013-10-01 10:31:04 +00:00
Daniel Sanders
6ffe6fc99c
[mips][msa] Added support for matching mod_[us] from normal IR (i.e. not intrinsics)
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llvm-svn: 191737
2013-10-01 10:22:35 +00:00
Richard Sandiford
ffc286beba
Fix pattern sort in DAGISelEmitter.cpp
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The old code skipped one of the sorting criteria if either pattern had
no types. This could lead to cycles of the form X < Y, Y < Z, Z < X.
llvm-svn: 191735
2013-10-01 09:49:01 +00:00
Vladimir Medic
fe4fd5260f
This patch adds aliases for Mips sub instruction with immediate operands. Corresponding test cases are added.
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llvm-svn: 191734
2013-10-01 09:48:56 +00:00
Elena Demikhovsky
84c6cd222d
AVX-512: Added X86vzmovl patterns
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llvm-svn: 191733
2013-10-01 08:38:02 +00:00
Craig Topper
e1e883da01
Remove 0 as a valid encoding for the m-mmmm field.
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llvm-svn: 191732
2013-10-01 07:10:28 +00:00
Craig Topper
419f67b3cc
Remove unneeded fields from disassembler internal instruction format.
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llvm-svn: 191731
2013-10-01 06:56:57 +00:00
Craig Topper
401688a9b1
BEXTR should be defined to take same type for bother operands.
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llvm-svn: 191728
2013-10-01 03:48:26 +00:00
Tom Stellard
1e84b314be
SelectionDAG: Clarify comments from r191600
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llvm-svn: 191724
2013-10-01 02:09:00 +00:00
Andrew Kaylor
6f0e782b64
Tests for MCJIT multiple module support
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llvm-svn: 191723
2013-10-01 01:48:36 +00:00
Andrew Kaylor
b068069d0c
Adding multiple module support for MCJIT.
...
Tests to follow.
PIC with small code model and EH frame handling will not work with multiple modules. There are also some rough edges to be smoothed out for remote target support.
llvm-svn: 191722
2013-10-01 01:47:35 +00:00
Eric Christopher
f7c4656096
Add the DW_AT_GNU_ranges_base attribute if we've emitted any ranges
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into the debug_ranges section.
llvm-svn: 191721
2013-10-01 00:43:36 +00:00
Eric Christopher
ff4531d2fa
Update comments.
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llvm-svn: 191720
2013-10-01 00:43:31 +00:00
Matt Arsenault
a3e171a6c8
Fix code duplication
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llvm-svn: 191716
2013-10-01 00:01:14 +00:00
Preston Gurd
182f111d29
Forgot to add a break statement.
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llvm-svn: 191715
2013-09-30 23:51:22 +00:00
Matt Arsenault
19f03c0f9c
Use CHECK-LABEL
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llvm-svn: 191713
2013-09-30 23:31:55 +00:00
Matt Arsenault
c27397065a
Reuse variable
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llvm-svn: 191712
2013-09-30 23:31:50 +00:00
Preston Gurd
a352cdea56
The X86FixupLEAs pass for Intel Atom must not call convertToThreeAddress
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on ADD16rr opcodes, if src1 != src, since that would cause
convertToThreeAddress to try to create a virtual register. This is not
permitted after register allocation, which is when the X86FixupLEAs pass
runs.
This patch fixes PR16785.
llvm-svn: 191711
2013-09-30 23:18:42 +00:00
Eric Christopher
d9670853b9
The DW_AT_GNU_pubnames/pubtypes attributes are actually form
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SEC_OFFSET from the beginning of the section so go ahead and emit
a label at the beginning of each one.
llvm-svn: 191710
2013-09-30 23:14:16 +00:00
Eric Christopher
aa86376c19
Add llvm-readobj to the list of programs to find in the freshly built
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toolchain.
Patch by Richard Pennington.
llvm-svn: 191706
2013-09-30 21:55:01 +00:00
Matt Arsenault
9b03bd2eff
Fix getOrInsertGlobal dropping the address space.
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Currently it will insert an illegal bitcast.
Arguably, the address space argument should be
added for the creation case.
llvm-svn: 191702
2013-09-30 21:23:03 +00:00
Matt Arsenault
bc0b70cd8d
Use right address space size in InstCombineCompares
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The test's output doesn't change, but this ensures
this is actually hit with a different address space.
llvm-svn: 191701
2013-09-30 21:11:01 +00:00
Matt Arsenault
27f5203bba
Constant fold ptrtoint + compare with address spaces
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llvm-svn: 191699
2013-09-30 21:06:18 +00:00
Manman Ren
1c604f3b2e
Debug Info: constify and rename from generateRef to getRef.
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No functionality change.
llvm-svn: 191696
2013-09-30 19:42:10 +00:00
Anders Waldenborg
df4432bb73
llvm-c: use typedef for function pointers
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This makes it consistent with other function pointers used in llvm-c
Differential Revision: http://llvm-reviews.chandlerc.com/D1712
llvm-svn: 191693
2013-09-30 19:11:32 +00:00
Tilmann Scheller
72c5c7344c
[ARM] Fix Thumb(-2) diagnostic tests.
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Changing the diagnostic message for out of range branch targets in 191686 broke the tests.
The diagnostic message for out of range branch targets was changed to be more consistent with the other diagnostics.
llvm-svn: 191691
2013-09-30 18:50:51 +00:00
Manman Ren
ad317a135a
TBAA: update tbaa format from scalar format to struct-path aware format.
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llvm-svn: 191690
2013-09-30 18:17:55 +00:00
Manman Ren
799fd39420
TBAA: remove !tbaa from testing cases when they are not needed.
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llvm-svn: 191689
2013-09-30 18:17:35 +00:00
Jack Carter
87696d33e7
[mips][msa] Direct Object Emission for I8 instructions.
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This patch adds Direct Object Emission support for I8 instructions: andi.b, bmnzi.b, bmzi.b, bseli.b, nori.b, ori.b, shf.{b,h,w} and xori.b.
Patch by Matheus Almeida
llvm-svn: 191688
2013-09-30 18:05:18 +00:00
Jack Carter
ef8714ee72
[mips][msa] Direct Object Emission for I5 instructions.
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This patch adds Direct Object Emission support for I5 instructions: addvi.{b,h,w,d}, ceqi.{b,h,w,d}, clei_s.{b,h,w,d}, clei_u.{b,h,w,d}, clti_s.{b,h,w,d}, clti_u.{b,h,w,d}, maxi_s.{b,h,w,d}, maxi_u.{b,h,w,d}, mini_s.{b,h,w,d}, mini_u.{b,h,w,d}, subvi.{b,h,w,d}.
Patch by Matheus Almeida
llvm-svn: 191687
2013-09-30 17:58:07 +00:00
Tilmann Scheller
8255c22a0e
[ARM] Clean up ARMAsmParser::validateInstruction().
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Fix some LLVM Coding Standards violations.
No changes in functionality.
llvm-svn: 191686
2013-09-30 17:57:30 +00:00
Jack Carter
edd6f0149e
[mips][msa] Direct Object Emission for 2R instructions.
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This patch adds Direct Object Emission support for 2R instructions: nloc.{b,h,w}, nlzc.{b,h,w}, pcnt.{b,w,d}.
Patch by Matheus Almeida
llvm-svn: 191685
2013-09-30 17:52:33 +00:00
Jack Carter
0d832949ac
[PATCH 1/4] [mips][msa] Source register of FILL instructions is GPR
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and not an MSA register
Patch by Matheus Almeida
llvm-svn: 191684
2013-09-30 17:43:04 +00:00
Tilmann Scheller
3f19743d37
[ARM] Use FileCheck instead of grep for ARM LDRD negative tests.
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llvm-svn: 191683
2013-09-30 17:31:26 +00:00
Rafael Espindola
c7fe26d6e4
Move command line options to the users of libLTO. Fixes --enable-shared build.
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Patch by Richard Sandiford.
llvm-svn: 191680
2013-09-30 16:39:19 +00:00
Rafael Espindola
bed99fa456
Revert "Enable building LTO on WIN32."
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This reverts commit r191670.
It was causing build failures on the msvc bots:
http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/5166/steps/compile/logs/stdio
llvm-svn: 191679
2013-09-30 16:32:51 +00:00
Tilmann Scheller
e69a5118c3
[ARM] Assembler: ARM LDRD with writeback requires the base register to be different from the destination registers.
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See ARM ARM A8.8.72.
Violating this constraint results in unpredictable behavior.
llvm-svn: 191678
2013-09-30 16:11:48 +00:00
Arnold Schwaighofer
a8d7eeffb9
Swift model: Fix uop description on some writes
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Those writes really need two/three uops.
llvm-svn: 191677
2013-09-30 15:56:34 +00:00
Benjamin Kramer
0b73a10aeb
BoundsChecking: Fix refacto.
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llvm-svn: 191676
2013-09-30 15:52:50 +00:00
Benjamin Kramer
7b5eaaacfd
Convert manual insert point restores to the new RAII object.
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llvm-svn: 191675
2013-09-30 15:40:17 +00:00
Benjamin Kramer
ae9249f56f
InstCombine: Replace manual fast math flag copying with the new IRBuilder RAII helper.
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Defines away the issue where cast<Instruction> would fail because constant
folding happened. Also slightly cleaner.
llvm-svn: 191674
2013-09-30 15:39:59 +00:00