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Commit Graph

90681 Commits

Author SHA1 Message Date
Justin Holewinski
2d5d17d8c6 [NVPTX] Fix handling of vector arguments
llvm-svn: 177847
2013-03-24 21:17:47 +00:00
Jakob Stoklund Olesen
191e5c7e77 Clean up Sparc patterns.
The types of register variables no longer need to be specified in output
patterns.

llvm-svn: 177845
2013-03-24 19:37:04 +00:00
Jakob Stoklund Olesen
b8c553e610 Allow types to be omitted in output patterns.
This syntax is now preferred:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

There is no reason to repeat the types in the output pattern.

llvm-svn: 177844
2013-03-24 19:37:00 +00:00
Jakob Stoklund Olesen
83c1b42b62 Allow TableGen DAG arguments to be just a name.
DAG arguments can optionally be named:

  (dag node, node:$name)

With this change, the node is also optional:

  (dag node, node:$name, $name)

The missing node is treated as an UnsetInit, so the above is equivalent
to:

  (dag node, node:$name, ?:$name)

This syntax is useful in output patterns where we currently require the
types of variables to be repeated:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr i32:$b, i32:$c)>;

This is preferable:

  def : Pat<(subc i32:$b, i32:$c), (SUBCCrr $b, $c)>;

llvm-svn: 177843
2013-03-24 19:36:51 +00:00
Tobias Grosser
589c56587c GettingStarted: Add Git clone instructions for compiler-rt and test-suite
Contributed-by:  Thomas Schwinge  <thomas@codesourcery.com>
llvm-svn: 177841
2013-03-24 15:15:19 +00:00
Jakub Staszak
760ea04733 Minor cleanups. No functionality change.
llvm-svn: 177837
2013-03-24 09:56:28 +00:00
Jakub Staszak
8c92d0d919 Use dyn_cast instead of isa && cast.
No functionality change.

llvm-svn: 177836
2013-03-24 09:25:47 +00:00
Jakob Stoklund Olesen
9e3f84b275 Give Sparc instruction patterns direct types instead of register classes.
Also update the documentation since Sparc is the nicest backend, and
used as an example in WritingAnLLVMBackend.

llvm-svn: 177835
2013-03-24 00:56:20 +00:00
Jakob Stoklund Olesen
2b502e642b Allow direct value types to be used in instruction 'set' patterns.
This makes it possible to define instruction patterns like this:

def LDri : F3_2<3, 0b000000,
                (outs IntRegs:$dst), (ins MEMri:$addr),
                "ld [$addr], $dst",
                [(set i32:$dst, (load ADDRri:$addr))]>;
                      ~~~

llvm-svn: 177834
2013-03-24 00:56:16 +00:00
Hal Finkel
744ce022d4 PPC ZERO register needs a register number of 0.
In order for the new ZERO register to be used with MC, etc. we need to specify
its register number (0).

Thanks to Kai for reporting the problem!

llvm-svn: 177833
2013-03-23 22:06:07 +00:00
Hal Finkel
f2651e5086 Note in PPCFunctionInfo VRSAVE spills
In preparation for using the new register scavenger capability for providing
more than one register simultaneously, specifically note functions that have
spilled VRSAVE (currently, this can happen only in functions that use the
setjmp intrinsic). As with CR spilling, such functions will need to provide two
emergency spill slots to the scavenger.

No functionality change intended.

llvm-svn: 177832
2013-03-23 22:06:03 +00:00
Hal Finkel
a0112219fe MCize the bcl instruction in PPCAsmPrinter
I recently added a BCL instruction definition as part of implementing SjLj
support. This can also be used to MCize bcl emission in the asm printer.

No functionality change intended.

llvm-svn: 177830
2013-03-23 20:53:15 +00:00
Jakob Stoklund Olesen
3a052b99b8 Use direct types in Sparc def : Pat patterns.
The SelectionDAG graph has MVT type labels, not register classes, so
this makes it clearer what is happening.

This notation is also robust against adding more types to the IntRegs
register class.

llvm-svn: 177829
2013-03-23 20:35:05 +00:00
Jakob Stoklund Olesen
332c7f8ecf Allow direct value types in pattern definitions.
Just like register classes, value types can be used in two ways in
patterns:

  (sext_inreg i32:$src, i16)

In a named leaf node like i32:$src, the value type simply provides the
type of the node directly. This simplifies type inference a lot compared
to the current practice of specifiying types indirectly with register
classes.

As an unnamed leaf node, like i16 above, the value type represents
itself as an MVT::Other immediate.

llvm-svn: 177828
2013-03-23 20:35:01 +00:00
Hal Finkel
ba870f6ed8 Cleanup some unused reg. scavenger parameters in PPCRegisterInfo
These spilling functions will eventually make use of the register scavenger,
however, they'll do so by taking advantage of PEI's virtual-register-based
delayed scavenging mechanism. As a result, these function parameters will not
be used, and can be removed.

No functionality change intended.

llvm-svn: 177827
2013-03-23 19:36:47 +00:00
Jakob Stoklund Olesen
a8e8e879c0 Make all unnamed RegisterClass TreePatternNodes typed MVT::i32.
A register class can appear as a leaf TreePatternNode with and without a
name:

  (COPY_TO_REGCLASS GPR:$src, F8RC)

In a named leaf node like GPR:$src, the register class provides type
information for the named variable represented by the node. The TypeSet
for such a node is the set of value types that the register class can
represent.

In an unnamed leaf node like F8RC above, the register class represents
itself as a kind of immediate. Such a node has the type MVT::i32,
we'll never create a virtual register representing it.

This change makes it possible to remove the special handling of
COPY_TO_REGCLASS in CodeGenDAGPatterns.cpp.

llvm-svn: 177825
2013-03-23 18:08:44 +00:00
Hal Finkel
8e322b7c0a Remove dead PPC LR spilling code
The LR register is unconditionally reserved, and its spilling and restoration
is handled by the prologue/epilogue code. As a result, it is never explicitly
spilled by the register allocator.

No functionality change intended.

llvm-svn: 177823
2013-03-23 17:14:27 +00:00
Benjamin Kramer
2d6ca3aea4 Plug a memory leak in FileCheck when the input file is empty.
llvm-svn: 177822
2013-03-23 13:56:23 +00:00
Benjamin Kramer
06ead4a9fa Move X86-dependent test into the right subdirectory.
llvm-svn: 177821
2013-03-23 09:35:44 +00:00
Owen Anderson
26a3518b43 Remove the type legality check from the SelectionDAGBuilder when it lowers @llvm.fmuladd to ISD::FMA nodes.
Performing this check unilaterally prevented us from generating FMAs when the incoming IR contained illegal vector types which would eventually be legalized to underlying types that *did* support FMA.
For example, an @llvm.fmuladd on an OpenCL float16 should become a sequence of float4 FMAs, not float4 fmul+fadd's.

NOTE: Because we still call the target-specific profitability hook, individual targets can reinstate the old behavior, if desired, by simply performing the legality check inside their callback hook.  They can also perform more sophisticated legality checks, if, for example, some illegal vector types can be productively implemented as FMAs, but not others.
llvm-svn: 177820
2013-03-23 08:26:53 +00:00
Michael Gottesman
0b8577b7d8 Change method name ClearRefCount => ClearKnownPositiveRefCount to match the name of the member that it is modifying.
llvm-svn: 177818
2013-03-23 05:46:19 +00:00
Michael Gottesman
a513e3e239 Changed the method name PtrState.IsKnownIncremented() to PtrState.HasKnownPositiveRefCount().
Now said method matches namewise every other method which refers to
the member KnownPositiveRefCount of the class PtrState.

llvm-svn: 177816
2013-03-23 05:31:01 +00:00
Hal Finkel
a9a4673757 Fix comparison of mixed signedness
177774 broke the lld-x86_64-darwin11 builder; error:
error: comparison of integers of different signs: 'int' and 'size_type' (aka 'unsigned long')
  for (SI = 0; SI < Scavenged.size(); ++SI)
               ~~ ^ ~~~~~~~~~~~~~~~~

Fix this by making SI also unsigned.

llvm-svn: 177780
2013-03-23 00:07:29 +00:00
Sean Silva
57d35d0952 [docs] Slight reword for precision.
The new wording cannot be construed as suggesting the use of
SmallVectorImpl<T> as e.g. a class member (just because the class
happens to be in an interface).

llvm-svn: 177778
2013-03-22 23:52:38 +00:00
Sean Silva
b845938bd3 [docs] Document usage of SmallVectorImpl in interfaces.
llvm-svn: 177775
2013-03-22 23:41:29 +00:00
Hal Finkel
2eaec9979f Allow the register scavenger to spill multiple registers
This patch lets the register scavenger make use of multiple spill slots in
order to guarantee that it will be able to provide multiple registers
simultaneously.

To support this, the RS's API has changed slightly: setScavengingFrameIndex /
getScavengingFrameIndex have been replaced by addScavengingFrameIndex /
isScavengingFrameIndex / getScavengingFrameIndices.

In forthcoming commits, the PowerPC backend will use this capability in order
to implement the spilling of condition registers, and some special-purpose
registers, without relying on r0 being reserved. In some cases, spilling these
registers requires two GPRs: one for addressing and one to hold the value being
transferred.

llvm-svn: 177774
2013-03-22 23:32:27 +00:00
Manman Ren
6e08f09d69 Support in AAEvaluator to print alias queries of loads/stores with TBAA tags.
Add "evaluate-tbaa" to print alias queries of loads/stores. Alias queries
between pointers do not include TBAA tags.

Add testing case for "placement new". TBAA currently says NoAlias.

llvm-svn: 177772
2013-03-22 22:34:41 +00:00
John McCall
d8ac46dfc7 Kill every call to @clang.arc.use in the ARC contract phase.
llvm-svn: 177769
2013-03-22 21:38:36 +00:00
Bill Wendling
59e6916b6b Update test. There may be multiple catches, but those will be cleaned up.
llvm-svn: 177758
2013-03-22 20:36:39 +00:00
Bill Wendling
aa052973d7 Add all clauses when merging the landing pads. Duplicates will be handled later on.
llvm-svn: 177757
2013-03-22 20:31:05 +00:00
David Blaikie
55942ffd01 Swap the DIFile in DILexicalBlockFile out for the raw name/directory pair
This is the last change in transitioning all DIScopes to have a common prefix.

llvm-svn: 177756
2013-03-22 20:18:46 +00:00
David Blaikie
43ccb69f6a reorder the fields in DILexicalBlockFile to match the common prefix for DIScopes
llvm-svn: 177754
2013-03-22 19:13:22 +00:00
Galina Kistanova
653ad5e533 Reverted r176374. In some cases the lit.site.cfg file does not get generated in tools/clang/tools/extra.
llvm-svn: 177751
2013-03-22 18:54:14 +00:00
Bill Wendling
dcde0efb22 Don't use the removed API.
llvm-svn: 177749
2013-03-22 18:49:53 +00:00
Bill Wendling
52cf114e8c Revert r177675. This is language-specific and shouldn't be in the API.
llvm-svn: 177748
2013-03-22 18:46:32 +00:00
Jyotsna Verma
fa7dec4e5b Hexagon: Add and enable memops setbit, clrbit, &,|,+,- for byte, short, and word.
llvm-svn: 177747
2013-03-22 18:41:34 +00:00
David Blaikie
c2fe0cb2ae Refactor out the DIFile parameter to DILexicalBlock to refer to the raw file/directory pair
llvm-svn: 177742
2013-03-22 17:33:20 +00:00
Eli Bendersky
7d1ea7b334 fix small doc typo
llvm-svn: 177737
2013-03-22 16:09:06 +00:00
Michel Danzer
dee420c03f R600: Fix up test/CodeGen/R600/llvm.pow.ll for r177730
llvm-svn: 177736
2013-03-22 15:24:16 +00:00
Ulrich Weigand
c069500748 Remove ABI-duplicated call instruction patterns.
We currently have a duplicated set of call instruction patterns depending
on the ABI to be followed (Darwin vs. Linux).  This is a bit odd; while the
different ABIs will result in different instruction sequences, the actual
instructions themselves ought to be independent of the ABI.  And in fact it
turns out that the only nontrivial difference between the two sets of
patterns is that in the PPC64 Linux ABI, the instruction used for indirect
calls is marked to take X11 as extra input register (which is indeed used
only with that ABI to hold an incoming environment pointer for nested
functions).  However, this does not need to be hard-coded at the .td
pattern level; instead, the C++ code expanding calls can simply add that
use, just like it adds uses for argument registers anyway.

No change in generated code expected.

llvm-svn: 177735
2013-03-22 15:24:13 +00:00
Ulrich Weigand
affdda3ea1 Rename memrr ptrreg and offreg components.
Currently, the sub-operand of a memrr address that corresponds to what
hardware considers the base register is called "offreg", while the
sub-operand that corresponds to the offset is called "ptrreg".

To avoid confusion, this patch simply swaps the named of those two
sub-operands and updates all uses.  No functional change is intended.

llvm-svn: 177734
2013-03-22 14:59:13 +00:00
Ulrich Weigand
c8c3c4dc22 Fix swapped BasePtr and Offset in pre-inc memory addresses.
PPCTargetLowering::getPreIndexedAddressParts currently provides
the base part of a memory address in the offset result, and the
offset part in the base result.  That swap is then undone again
when an MI instruction is generated (in PPCDAGToDAGISel::Select
for loads, and using .md Pat patterns for stores).

This patch reverts this double swap, to make common code and
back-end be in sync as to which part of the address is base
and which is offset.

To avoid performance regressions in certain cases, target code
now checks whether the choice of base register would be rejected
for pre-inc accesses by common code, and attempts to swap base
and offset again in such cases.  (Overall, this means that now
pre-ice accesses are generated *more* frequently than before.)

llvm-svn: 177733
2013-03-22 14:58:48 +00:00
Ulrich Weigand
4b7960b48d Tighten iaddroff ComplexPattern.
The iaddroff ComplexPattern is supposed to recognize displacement
expressions that have been processed by a SelectAddressRegImm,
which means it needs to accept TargetConstant and TargetGlobalAddress
nodes.  Currently, it erroneously also accepts some other nodes,
in particular Constant and PPCISD::Lo.

While this problem is currently latent, it would cause wrong-code
bugs with a follow-on patch I'm about to commit, so this patch
tightens the ComplexPattern.  The equivalent change is made in
PPCDAGToDAGISel::Select, where pre-inc load patterns are handled
(as opposed to store patterns, the loads are handled in C++ code
without making use of the .td ComplexPattern).

llvm-svn: 177732
2013-03-22 14:58:17 +00:00
Ulrich Weigand
27c5e0b210 Remove the xaddroff ComplexPattern.
The xaddroff pattern is currently (mistakenly) used to recognize
the *base* register in pre-inc store patterns.  This patch replaces
those uses by ptr_rc_nor0 (as is elsewhere done to match the base
register of an address), and removes the now unused ComplexPattern.

llvm-svn: 177731
2013-03-22 14:57:48 +00:00
Michel Danzer
2f63b04c7c R600: Use legacy (0 * anything = 0) MUL instructions for pow intrinsics
Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g.
manifested by failure of two piglit/glean tests and intermittent black
patches in many apps.

Tested on SI and RS880.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012 [radeonsi]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58150 [r600g]

NOTE: This is a candidate for the Mesa stable branch.

Reviewed-by: Christian König <christian.koenig@amd.com>
llvm-svn: 177730
2013-03-22 14:09:10 +00:00
Kostya Serebryany
3d0691a059 [asan] Change the way we report the alloca frame on stack-buff-overflow.
Before: the function name was stored by the compiler as a constant string
and the run-time was printing it.
Now: the PC is stored instead and the run-time prints the full symbolized frame.
This adds a couple of instructions into every function with non-empty stack frame,
but also reduces the binary size because we store less strings (I saw 2% size reduction).
This change bumps the asan ABI version to v3.

llvm part.

Example of report (now):
==31711==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x7fffa77cf1c5 at pc 0x41feb0 bp 0x7fffa77cefb0 sp 0x7fffa77cefa8
READ of size 1 at 0x7fffa77cf1c5 thread T0
    #0 0x41feaf in Frame0(int, char*, char*, char*) stack-oob-frames.cc:20
    #1 0x41f7ff in Frame1(int, char*, char*) stack-oob-frames.cc:24
    #2 0x41f477 in Frame2(int, char*) stack-oob-frames.cc:28
    #3 0x41f194 in Frame3(int) stack-oob-frames.cc:32
    #4 0x41eee0 in main stack-oob-frames.cc:38
    #5 0x7f0c5566f76c (/lib/x86_64-linux-gnu/libc.so.6+0x2176c)
    #6 0x41eb1c (/usr/local/google/kcc/llvm_cmake/a.out+0x41eb1c)
Address 0x7fffa77cf1c5 is located in stack of thread T0 at offset 293 in frame
    #0 0x41f87f in Frame0(int, char*, char*, char*) stack-oob-frames.cc:12  <<<<<<<<<<<<<< this is new
  This frame has 6 object(s):
    [32, 36) 'frame.addr'
    [96, 104) 'a.addr'
    [160, 168) 'b.addr'
    [224, 232) 'c.addr'
    [288, 292) 's'
    [352, 360) 'd'

llvm-svn: 177724
2013-03-22 10:37:20 +00:00
Dmitry Vyukov
b12c1b7911 tsan: fix the test
Add missed file from r177717 commit that adds __tsan_vptr_read.

llvm-svn: 177719
2013-03-22 09:04:01 +00:00
Dmitry Vyukov
eae8006130 tsan: handle vptr loads specially
This is required to determine ctor/dtor vs virtual call races.
http://llvm-reviews.chandlerc.com/D566

llvm-svn: 177717
2013-03-22 08:51:22 +00:00
Evgeniy Stepanov
f128dbc036 Fix llvm::removeUnreachableBlocks to handle unreachable loops.
llvm-svn: 177713
2013-03-22 08:43:04 +00:00
Arnaud A. de Grandmaison
7a4226244b InstCombine: Improve the result bitvect type when folding (cmp pred (load (gep GV, i)) C) to a bit test.
The original code used i32, and i64 if legal. This introduced unneeded
casts when they aren't legal, or when the index variable i has another
type. In order of preference: try to use i's type; use the smallest
fitting legal type (using an added DataLayout method); default to i32.
A testcase checks that this works when the index gep operand is i16.

Patch by : Ahmed Bougacha <ahmed.bougacha@gmail.com>
Reviewed by : Duncan

llvm-svn: 177712
2013-03-22 08:25:01 +00:00