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Commit Graph

131312 Commits

Author SHA1 Message Date
Justin Bogner
6d6bd1c06e CMake: generate check targets for lit suites without their own lit.cfgs
Currently our cmake generates targets like check-llvm-unit and
check-llvm-transforms-loopunroll-x86, but not check-llvm-transforms or
check-llvm-transforms-adce. This is because the search for test suites
only lists the ones with a custom lit.cfg or lit.local.cfg.

Instead, we can do something a little smarter - any directory under
test that isn't called Inputs or inside a directory called Inputs is a
test suite.

llvm-svn: 268806
2016-05-06 21:57:30 +00:00
Matthias Braun
9b767099e0 LiveIntervalAnalysis: Fix handleMove() extending liverange for undef inputs
Fix handleMove() incorrectly extending liveranges when an undef input of
a vreg was moved past the (current) end of the liverange.

llvm-svn: 268805
2016-05-06 21:47:41 +00:00
Philip Reames
751f932d9a [GVN] PRE of unordered loads
Again, fairly simple.  Only change is ensuring that we actually copy the property of the load correctly.  The aliasing legality constraints were already handled by the FRE patches.  There's nothing special about unorder atomics from the perspective of the PRE algorithm itself.

llvm-svn: 268804
2016-05-06 21:43:51 +00:00
Simon Pilgrim
e784303c41 [SLPVectorizer][X86] Added BSWAP/BITREVERSE vectorization tests
llvm-svn: 268803
2016-05-06 21:41:55 +00:00
Simon Pilgrim
0b1b8f9a44 [SLPVectorizer][X86] Added CTPOP/CTLZ/CTTZ vectorization tests
llvm-svn: 268800
2016-05-06 21:33:01 +00:00
Quentin Colombet
b57548ebe3 Revert "[X86] Add a new LOW32_ADDR_ACCESS_RBP register class."
This reverts commit r268796.
I believe it breaks test/CodeGen/X86/asm-mismatched-types.ll with:
Cannot emit physreg copy instruction

llvm-svn: 268799
2016-05-06 21:21:50 +00:00
Zachary Turner
09bbd58bad Fix failing test due to merge conflict.
llvm-svn: 268798
2016-05-06 21:19:29 +00:00
Quentin Colombet
8fff738643 [X86] Add a new LOW32_ADDR_ACCESS_RBP register class.
ABIs like NaCl uses 32-bit addresses but have 64-bit frame.
The new register class reflects those constraints when choosing a
register class for a address access.

llvm-svn: 268796
2016-05-06 21:10:53 +00:00
Quentin Colombet
e9b1078e26 [X86] Rename the X32_ADDR_ACCESS register class into LOW32_ADDR_ACCESS.
This register class may be used by any ABIs that uses x86_64 ISA while
using 32-bit addresses, not just in X32 cases. Make sure the name
reflects that.

llvm-svn: 268795
2016-05-06 21:10:43 +00:00
Nico Weber
76b0c74859 Revert r268760, it caused PR27670.
llvm-svn: 268794
2016-05-06 21:07:02 +00:00
Zachary Turner
37493811fd Add missing include.
llvm-svn: 268792
2016-05-06 20:59:35 +00:00
Zachary Turner
9a2aa250f9 Port DebugInfoPDB over to using llvm::Error.
Differential Revision: http://reviews.llvm.org/D19940
Reviewed By: rnk

llvm-svn: 268791
2016-05-06 20:51:57 +00:00
Sanjoy Das
4ad33c5c70 [RS4GC] Fix typo in comment
llvm-svn: 268790
2016-05-06 20:39:33 +00:00
Kevin Enderby
ee96ce6849 Change GenericBinaryError to no longer include a FileName, which is then not
part of the error message.

As the caller is the one that needs to add the name of where the "object file"
comes from to the error message as the object file could be in an archive, or
coming from a slice of a Mach-O universal file or a buffer created by a JIT.

In the cases of a Mach-O universal file the architecture name may or may not
also need to be printed which is up to the tool code.  For example if the tool
code is only selecting the host architecture slice then that architecture name
is never printed.

This patch is the change to the libObject code and there will be follow on
commits for changes to the code for each tool.

llvm-svn: 268789
2016-05-06 20:16:28 +00:00
Kostya Serebryany
b29cae8463 [libFuzzer] more trophies
llvm-svn: 268788
2016-05-06 20:14:48 +00:00
Ahmed Bougacha
b21c6806a5 [X86] Accept imp-defs of GR64 super-registers in FixupBW MOVrr.
Testcase will follow shortly.

llvm-svn: 268787
2016-05-06 20:03:03 +00:00
Marcin Koscielnicki
181dd83a14 [MSan] [X86] Fix vararg helper for fixed arguments in overflow area.
This fixes http://llvm.org/PR27646 on x86_64.

Differential Revision: http://reviews.llvm.org/D19997

llvm-svn: 268783
2016-05-06 19:36:56 +00:00
Artem Tamazov
d5f00a9b9b [AMDGPU][llvm-mc] Some refactoring of .td files
Some custom Operands and AsmOperandClasses moved to proper place.
No functional changes.

Differential Revision: http://reviews.llvm.org/D20012

llvm-svn: 268780
2016-05-06 19:32:38 +00:00
Adrian Prantl
4cae5e1ced Refactor the Verifier so it can diagnose IR validation errors and debug
info metadata errors separately. (NFC)

This patch refactors the Verifier so it can diagnose IR validation errors
and debug info metadata errors separately.
The motivation behind this change is that broken (or outdated) debug info
can be "recovered" from by stripping the debug info.

The problem I'm trying to solve with this sequence of patches is that
historically we've done a really bad job at verifying debug info.
We want to be able to make the verifier stricter without having to worry
about breaking bitcode compatibility with existing producers. For example,
we don't necessarily want IR produced by an older version of clang to be
rejected by an LTO link just because of malformed debug info, and rather
provide an option to strip it. Note that merely outdated (but well-formed)
debug info would continue to be auto-upgraded in this scenario.

http://reviews.llvm.org/D19986
rdar://problem/25818489

llvm-svn: 268778
2016-05-06 19:26:47 +00:00
Krzysztof Parzyszek
37a28def86 [Hexagon] Be careful about anti-dependencies with a call in packetizer
In a case like
  J2_callr <ga:@foo>, %R0<imp-use>, ...
  R0<def> = ...
the anti-dependency on R0 cannot be ignored and the two instructions
cannot be packetized together, since if they were, the assignment to
R0 would take place before the call.

llvm-svn: 268776
2016-05-06 19:13:38 +00:00
Philip Reames
dc0f8cd8d4 [GVN] Handle unordered atomics in cross block FRE
You'll note there are essentially no code changes here.  Cross block FRE heavily reuses code from the block local FRE.  All of the tricky parts were done as part of the previous patch and the refactoring that removed the original code duplication.  

llvm-svn: 268775
2016-05-06 18:46:45 +00:00
Justin Bogner
a6d97fe150 SDAG: Don't leave dangling dead nodes after SelectCodeCommon
Relying on the caller to clean up after we've replaced all uses of a
node won't work when we've migrated to the `void Select(...)` API.

llvm-svn: 268774
2016-05-06 18:42:16 +00:00
Eric Christopher
52aaa2fdc5 The associated PR for this test was PR27135 not PR27132.
llvm-svn: 268772
2016-05-06 18:23:14 +00:00
Quentin Colombet
1c4bd3fb04 [X86] Get rid of X32_NOREX_ADDR_ACCESS register class.
According to H.J. Lu <hjl.tools@gmail.com>, this register class is never
used.

llvm-svn: 268771
2016-05-06 18:22:48 +00:00
Philip Reames
8b344ddfa7 [GVN] Do local FRE for unordered atomic loads
This patch is the first in a small series teaching GVN to optimize unordered loads aggressively. This change just handles block local FRE because that's the simplest thing which lets me test MDA, and the AvailableValue pieces. Somewhat suprisingly, MDA appears fine and only a couple of small changes are needed in GVN.

Once this is in, I'll tackle non-local FRE and PRE. The former looks like a natural extension of this, the later will require a couple of minor changes.

Differential Revision: http://reviews.llvm.org/D19440

llvm-svn: 268770
2016-05-06 18:17:13 +00:00
Mehdi Amini
e4d2c8bb3a Tweak the ThinLTO pass pipeline
Summary:
The original ThinLTO pipeline was derived from some
work I did tuning FullLTO on the test suite and SPEC. This
patch reduces the amount of work done in the "linker phase" of
the build, and extend the function simplifications passes
performed during the "compile phase". This helps the build time
by reducing the IR as much as possible during the compile phase
and limiting the work to be performed during the "link phase",
while keeping the performance "on par" with the existing pipeline.

Reviewers: tejohnson

Subscribers: llvm-commits, joker.eph

Differential Revision: http://reviews.llvm.org/D19773

From: Mehdi Amini <mehdi.amini@apple.com>
llvm-svn: 268769
2016-05-06 18:17:03 +00:00
Sanjay Patel
791dd3587c [SimplifyCFG] propagate branch metadata when creating select (retry r268550 / r268751 with possible fix)
Retrying r268550/r268751 which were reverted at r268577/r268765 due a memory sanitizer failure.
I have not been able to reproduce that failure, but I've taken another guess at fixing
the problem in this version of the patch and will watch for another failure.

Original commit message:
Unlike earlier similar fixes, we need to recalculate the branch weights
in this case.

Differential Revision: http://reviews.llvm.org/D19674

llvm-svn: 268767
2016-05-06 18:07:46 +00:00
Sanjay Patel
3ebfb989c8 revert r268751 - caused same failures on msan bot
llvm-svn: 268765
2016-05-06 17:51:37 +00:00
Simon Pilgrim
2ec2e6178f [CostModel][X86] Tweak 'SSE2-only' test CPU as it was only disabling SSE41 not SSE3/SSSE3 etc.
llvm-svn: 268763
2016-05-06 17:50:07 +00:00
Artem Tamazov
1adac220b3 [AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.
Added support for sendmsg(MSG[, OP[, STREAM_ID]]) syntax
in s_sendmsg and s_sendmsghalt instructions.
The syntax matches the SP3 assembler/disassembler rules.
That is why implicit inputs (like M0 and EXEC) are not printed
to disassembly output anymore.

sendmsg(...) allows only known message types and attributes,
even if literals are used instead of symbolic names.
However, raw literal (without "sendmsg") still can be used,
and that allows for any 16-bit value.

Tests updated/added.

Differential Revision: http://reviews.llvm.org/D19596

llvm-svn: 268762
2016-05-06 17:48:48 +00:00
Simon Pilgrim
2fab54a682 [CostModel][X86] Added ctlz/cttz undef-zero costmodel tests
llvm-svn: 268761
2016-05-06 17:48:35 +00:00
Ahmed Bougacha
ad072149c6 [X86] Teach X86FixupBWInsts to promote MOV8rr/MOV16rr to MOV32rr.
Codesize is less (16) or equal (8), and we avoid partial dependencies.

Differential Revision: http://reviews.llvm.org/D19999

llvm-svn: 268760
2016-05-06 17:42:57 +00:00
Ahmed Bougacha
a16ae14466 [X86] Remove \brief in FixupBW. NFC.
llvm-svn: 268754
2016-05-06 17:28:47 +00:00
Ahmed Bougacha
ff9ea6cac5 [X86] Simplify FixupBW sub_8bit_hi-related logic. NFC.
Instead of passing around sizes and asking for subregs, we can check
the subreg indices we care about: sub_8bit_hi and sub_8bit.

Differential Revision: http://reviews.llvm.org/D20006

llvm-svn: 268753
2016-05-06 17:28:42 +00:00
Geoff Berry
8ea40e4920 [AArch64] Fix test to specify triple and disable post-RA scheduling.
This should fix bot breakage caused by r268746:
[AArch64] Combine callee-save and local stack SP adjustment instructions.

llvm-svn: 268752
2016-05-06 17:12:38 +00:00
Sanjay Patel
751f2c7137 [SimplifyCFG] propagate branch metadata when creating select (retry r268550 with possible fix)
Retrying r268550 which was reverted at r268577 due a memory sanitizer failure.
I have not been able to reproduce that failure, but I've taken a guess at fixing
the problem in this version of the patch and will watch for another failure.

Original commit message:
Unlike earlier similar fixes, we need to recalculate the branch weights
in this case.

Differential Revision: http://reviews.llvm.org/D19674

llvm-svn: 268751
2016-05-06 17:07:47 +00:00
Geoff Berry
8681d4c5a2 [AArch64] Combine callee-save and local stack SP adjustment instructions.
Summary:
If a function needs to allocate both callee-save stack memory and local
stack memory, we currently decrement/increment the SP in two steps:
first for the callee-save area, and then for the local stack area.  This
changes the code to allocate them both at once at the very beginning/end
of the function.  This has two benefits:

1) there is one fewer sub/add micro-op in the prologue/epilogue

2) the stack adjustment instructions act as a scheduling barrier, so
moving them to the very beginning/end of the function increases post-RA
scheduler's ability to move instructions (that only depend on argument
registers) before any of the callee-save stores

This change can cause an increase in instructions if the original local
stack SP decrement could be folded into the first store to the stack.
This occurs when the first local stack store is to stack offset 0.  In
this case we are trading off one more sub instruction for one fewer sub
micro-op (along with benefits (2) and (3) above).

Reviewers: t.p.northover

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D18619

llvm-svn: 268746
2016-05-06 16:34:59 +00:00
Jun Bum Lim
071a2f76d8 [AArch64] Decouple zero store promotion from narrow ld merge. NFC.
Summary: This change refactors to decouple the zero store promotion from the narrow ld merge and add a flag (enable-narrow-ld-merge=true) to control the narrow ld merge optimization.

Reviewers: jmolloy, t.p.northover, mcrosier

Subscribers: aemerson, rengolin, mcrosier, llvm-commits

Differential Revision: http://reviews.llvm.org/D19885

llvm-svn: 268744
2016-05-06 15:08:57 +00:00
Nikolay Haustov
1bdab4f693 Revert "AMDGPU/SI: Add amdgpu_kernel calling convention. Part 2."
This reverts commit 47486d52454d60cdf6becc0b2efe533c73794380.

It broke calling OpenCL kernel from another kernel.

llvm-svn: 268739
2016-05-06 14:59:04 +00:00
Simon Pilgrim
55d3667833 [CostModel][X86] Added costmodel tests for vector ctpop/ctlz/cttz/bitreverse/bswap
llvm-svn: 268738
2016-05-06 14:38:14 +00:00
Daniel Sanders
9b9d5f9f6f [mips] Fix inconsistent .cprestore behaviour between direct object emission and assembling.
Summary:
Direct object emission has an initialization order problem where an
InitMCObjectFile is called after MipsTargetELFStreamer determines whether
PIC is enabled by default or not. There doesn't seem to be point that
initializes all cases so split the responsibility between
MipsTargetELFStreamer and MipsAsmPrinter.

Reviewers: sdardis

Subscribers: dsanders, llvm-commits, sdardis

Differential Revision: http://reviews.llvm.org/D19728

llvm-svn: 268737
2016-05-06 14:37:24 +00:00
Chad Rosier
0032771b5a [SimplifyCFG] Prefer a simplification based on a dominating condition.
Rather than merge two branches with a common destination.
Differential Revision: http://reviews.llvm.org/D19743

llvm-svn: 268735
2016-05-06 14:25:14 +00:00
Daniel Sanders
cd4dc5cad8 [mips] Correct the ordering of HI/LO pairs in the relocation table.
Summary:
There seems to have been a misunderstanding as to the meaning of 'offset' in
the rules laid down by our ABI. The previous code believed that 'offset' meant
the offset within the section that the relocation is applied to. However, it
should have meant the offset from the symbol used in the relocation expression.

This patch adds two fields to ELFRelocationEntry and uses them to correct the
order of relocations for MIPS. These fields contain:
* The original symbol before shouldRelocateWithSymbol() is considered. This
  ensures that R_MIPS_GOT16 is able to correctly distinguish between local and
  external symbols, allowing us to tell whether %got() requires a matching
  %lo() or not (local symbols require one, external symbols don't). It also
  prevents confusing cases where the fuzzy matching rules cause things like
  %hi(foo)/%lo(foo+3) and %hi(bar)/%lo(bar+1) to swap their %lo()'s.
* The original offset before shouldRelocateWithSymbol() is considered. The
  existing Addend field is always zero when the object uses in place addends
  (because it's already moved it to the encoding) but MIPS needs to use the
  original offset to ensure that the linker correctly calculates the carry-in
  bit for %hi() and %got().

IAS ensures that unmatchable %hi()/%got() relocations are placed at the end of
the table to ensure that the linker rejects the table (we're unable to report
such errors directly). The alternatives to this risk accidental matching
against inappropriate relocations which may silently compute incorrect values
due to an incorrect carry bit between the %lo() and %hi()/%got().

Reviewers: sdardis

Subscribers: dsanders, sdardis, rafael, llvm-commits

Differential Revision: http://reviews.llvm.org/D19718

llvm-svn: 268733
2016-05-06 13:49:25 +00:00
Daniel Sanders
ae8df9e819 [mips][mips16] Use isUnconditionalBranch() in AnalyzeBranch() and constant island pass.
Summary:
This stops it misidentifying unconditional branches as conditional branches
which fixes a -verify-machineinstrs error about exiting a function via fall through.

Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19864

llvm-svn: 268731
2016-05-06 13:23:51 +00:00
Daniel Sanders
198717c89c [mips][fastisel] Conditional moves do not have implicit operands.
Reviewers: sdardis

Subscribers: dsanders, sdardis, llvm-commits

Differential Revision: http://reviews.llvm.org/D19862

llvm-svn: 268730
2016-05-06 12:57:26 +00:00
Sam Kolton
6ae1dde4c7 [TableGen] AsmMatcher: support for default values for optional operands
Summary:
This change allows to specify "DefaultMethod" for optional operand (IsOptional = 1) in AsmOperandClass that return default value for operand. This is used in convertToMCInst to set default values in MCInst.
Previously if you wanted to set default value for operand you had to create custom converter method. With this change it is possible to use standard converters even when optional operands presented.

Reviewers: tstellarAMD, ab, craig.topper

Subscribers: jyknight, dsanders, arsenm, nhaustov, llvm-commits

Differential Revision: http://reviews.llvm.org/D18242

llvm-svn: 268726
2016-05-06 11:31:17 +00:00
Ryan Govostes
983694f354 Fix whitespace and line wrapping. NFC.
llvm-svn: 268725
2016-05-06 11:22:11 +00:00
Ryan Govostes
55b75f3fca [asan] add option to set shadow mapping offset
Allowing overriding the default ASAN shadow mapping offset with the
-asan-shadow-offset option, and allow zero to be specified for both offset and
scale.

Patch by Aaron Carroll <aaronc@apple.com>.

llvm-svn: 268724
2016-05-06 10:25:22 +00:00
Dylan McKay
3be6c5786f [AVR] Add a majority of the backend code
Summary: This adds the majority of the AVR backend.

Reviewers: hfinkel, dsanders, vkalintiris, arsenm

Subscribers: dylanmckay

Differential Revision: http://reviews.llvm.org/D17906

llvm-svn: 268722
2016-05-06 10:12:31 +00:00
Silviu Baranga
725ddde257 Attempt to fix the modules builder by declaring SCEV in LoopUtils.h
llvm-svn: 268720
2016-05-06 09:37:14 +00:00