Tobias Grosser
52e991f3dd
Update autoconf/automake versions in the documentation to match the versions used in Autogen.sh
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llvm-svn: 104113
2010-05-19 07:00:17 +00:00
Daniel Dunbar
8d60e90859
MC/X86: Lower MOV{8,16,32,64}{rm,mr} to fixed-register forms, as appropriate.
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llvm-svn: 104112
2010-05-19 06:20:44 +00:00
Evan Cheng
0aa58d5b69
Mark pattern-less mayLoad / mayStore instructions neverHasSideEffects. These do not have other un-modeled side effects.
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llvm-svn: 104111
2010-05-19 06:07:03 +00:00
Evan Cheng
b7657dfa38
Target instruction selection should copy memoperands.
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llvm-svn: 104110
2010-05-19 06:06:09 +00:00
Daniel Dunbar
b5277e8ca0
MC/X86: Strip spurious operands from CALL64r as we do for CALL64pcrel32, to
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avoid same prefix byte problem as in r104062.
llvm-svn: 104108
2010-05-19 04:31:36 +00:00
Evan Cheng
23fb523b44
Mark a few more pattern-less instructions with neverHasSideEffects. This is especially important on instructions like t2LEApcreal which are prime candidate for machine LICM.
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llvm-svn: 104102
2010-05-19 01:52:25 +00:00
Dan Gohman
434b54846d
Add a comment explaining why this code uses Append mode.
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llvm-svn: 104095
2010-05-19 01:21:34 +00:00
Evan Cheng
632cb17357
Intrinsics which do a vector compare (results are all zero or all ones) are modeled as icmp / fcmp + sext. This is turned into a vsetcc by dag combine (yes, not a good long term solution). The targets can then isel the vsetcc to the appropriate instruction.
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The trouble arises when the result of a vector cmp + sext is then and'ed with all ones. Instcombine will turn it into a vector cmp + zext, dag combiner will miss turning it into a vsetcc and hell breaks loose after that.
Teach dag combine to turn a vector cpm + zest into a vsetcc + and 1. This fixes rdar://7923010.
llvm-svn: 104094
2010-05-19 01:08:17 +00:00
Dan Gohman
f3685dcdc9
Factor out the code for picking integer arithmetic with immediate
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opcodes into a helper function. This fixes a few places in the code
which were not properly selecting the 8-bit-immediate opcodes.
llvm-svn: 104091
2010-05-19 00:53:19 +00:00
Eric Christopher
aec869777c
Add a test to make sure that we're lowering the shift amount correctly.
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llvm-svn: 104090
2010-05-19 00:22:04 +00:00
Dan Gohman
cdb7b1c110
Add a comment.
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llvm-svn: 104089
2010-05-18 23:55:57 +00:00
Dan Gohman
d81303e044
Fix the predicate which checks for non-sensical formulae which have
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constants in registers which partially cancel out their immediate fields.
llvm-svn: 104088
2010-05-18 23:48:08 +00:00
Dan Gohman
3a470a6b6c
Factor out the code for recomputing an LSRUse's Regs set after some
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of its formulae have been removed into a helper function, and also
teach it how to update the RegUseTracker.
llvm-svn: 104087
2010-05-18 23:42:37 +00:00
Bob Wilson
4872944eb3
Fix a crash when debugging the coalescer. DebugValue instructions are not
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in the coalescer's instruction map.
llvm-svn: 104086
2010-05-18 23:19:42 +00:00
Dan Gohman
a58ace4036
Factor out code for estimating search space complexity into a helper
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function.
llvm-svn: 104082
2010-05-18 22:51:59 +00:00
Dan Gohman
60d6263fde
Add some more debug output.
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llvm-svn: 104080
2010-05-18 22:41:32 +00:00
Dan Gohman
22ae418189
Factor out the code for deleting a formula from an LSRUse into
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a helper function.
llvm-svn: 104079
2010-05-18 22:39:15 +00:00
Dan Gohman
9c986cbbe9
Make some debug output more informative.
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llvm-svn: 104078
2010-05-18 22:37:37 +00:00
Dan Gohman
2a14bbdf13
Print an error message in Formula::print if the HasBaseReg flag
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is inconsistent with the BaseRegs field. It's not print's job to
assert on an invalid condition, but it can make one more obvious.
llvm-svn: 104077
2010-05-18 22:35:55 +00:00
Dan Gohman
649a99b8e8
Rename RegUseTracker's RegUses member to RegUsesMap to avoid
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confusion with LSRInstance's RegUses member.
llvm-svn: 104076
2010-05-18 22:33:00 +00:00
Jakob Stoklund Olesen
f3114dbb3a
Remember to update VirtRegLastUse when spilling without killing before a call.
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llvm-svn: 104074
2010-05-18 22:20:09 +00:00
Dan Gohman
42a89be283
Teach mode load folding and unfolding code about CMP32ri8 and friends.
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llvm-svn: 104068
2010-05-18 21:54:15 +00:00
Bill Wendling
5f00aa7459
Don't eliminate frame pointers from leaf functions if "--disable-fp-elim" is
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specified.
llvm-svn: 104066
2010-05-18 21:47:08 +00:00
Dan Gohman
eaa3ee65bd
When converting a test to a cmp to fold a load, use the cmp that has an
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8-bit immediate field rather than one with a wider immediate field.
llvm-svn: 104064
2010-05-18 21:42:03 +00:00
Eric Christopher
79cbb29471
Quick test to make sure we're emitting the tbss section correctly.
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llvm-svn: 104063
2010-05-18 21:40:20 +00:00
Chris Lattner
b1e6d120fc
make mcinstlower remove all but the first operand to CALL64pcrel32.
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The register use operands (e.g. the first argument is passed in a
register) is currently being modeled as a normal register use,
instead of correctly being an implicit use. This causes the operand
to get propagated onto the mcinst, which was causing the encoder to
emit a rex prefix byte, which generates an invalid call.
This fixes rdar://7998435
llvm-svn: 104062
2010-05-18 21:40:18 +00:00
Evan Cheng
e2980af336
Sink dag combine's post index load / store code that swap base ptr and index into the target hook. Only the target knows whether the swap is safe. In Thumb2 mode, the offset must be an immediate. rdar://7998649
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llvm-svn: 104060
2010-05-18 21:31:17 +00:00
Eric Christopher
3f0aa8bf21
Implement EmitTBSSSymbol for MachOStreamer.
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Fixes build failure as well.
llvm-svn: 104059
2010-05-18 21:26:41 +00:00
mike-m
f12653f97d
Fix enum to address array bounds regression.
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llvm-svn: 104058
2010-05-18 21:22:12 +00:00
Eric Christopher
4a9013f115
Make EmitTBSSSymbol take a section argument so that we can find it later.
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Fix up callers and users.
llvm-svn: 104057
2010-05-18 21:16:04 +00:00
Jakob Stoklund Olesen
1d0a54cb9d
Properly handle multiple definitions of a virtual register in the same
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instruction.
This can happen on ARM:
>> %reg1035:5<def>, %reg1035:6<def> = VLD1q16 %reg1028, 0, pred:14, pred:%reg0
Regs: Q0=%reg1032* R0=%reg1028* R1=%reg1029* R2 R3=%reg1031*
Killing last use: %reg1028
Allocating %reg1035 from QPR
Assigning %reg1035 to Q1
<< %D2<def>, %D3<def> = VLD1q16 %R0<kill>, 0, pred:14, pred:%reg0, %Q1<imp-def>
llvm-svn: 104056
2010-05-18 21:10:50 +00:00
Dale Johannesen
6b88a14922
Test passed on ppc, to my surprise; if it worked
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there it may work everywhere...
llvm-svn: 104053
2010-05-18 20:47:04 +00:00
Evan Cheng
dae4e9e4bc
Continuously refine the register class of REG_SEQUENCE def with all the source registers and sub-register indices.
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llvm-svn: 104051
2010-05-18 20:07:47 +00:00
Evan Cheng
9fc34e676d
Fix PR7162: Use source register classes and sub-indices to determine the correct register class of the definitions of REG_SEQUENCE.
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llvm-svn: 104050
2010-05-18 20:03:28 +00:00
Dale Johannesen
00e3e62df1
Testcase for llvm-gcc checkin 104042.
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llvm-svn: 104043
2010-05-18 19:03:51 +00:00
Kevin Enderby
cd585da505
Incorporate Daniel's suggestion and use !isdigit(CurPtr[0]) and not
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CurPtr[0] == '\n' when testing the character after a "0b" when looking
to see if it part of a something like "jmp 0b".
llvm-svn: 104039
2010-05-18 18:09:20 +00:00
Kevin Enderby
438a36f66a
Fixed the problem with a branch to "0b" that was not parsed by llvm-mc
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correctly. The Lexer was incorrectly eating the newline casusing it to branch
to address 0. Updated the test case to use a "0:" label and a branch to "0b".
llvm-svn: 104038
2010-05-18 17:51:35 +00:00
Jakob Stoklund Olesen
76a5a71473
Teach the machine code verifier to use getSubRegisterRegClass().
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The old approach was wrong. It had an off-by-one error.
llvm-svn: 104034
2010-05-18 17:31:12 +00:00
Daniel Dunbar
739e720a21
MC/Mach-O: Implement support for setting indirect symbol table offset in section header.
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Also, create symbol data for LHS of assignment, to match 'as' symbol ordering better.
llvm-svn: 104033
2010-05-18 17:28:24 +00:00
Daniel Dunbar
9a1bbd9dc5
MC/Mach-O: Remove some FIXMEs.
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llvm-svn: 104032
2010-05-18 17:28:20 +00:00
Daniel Dunbar
5ed90337ff
MC/Mach-O: Fail faster/harder when we see .file, which isn't yet supported.
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llvm-svn: 104031
2010-05-18 17:28:17 +00:00
Daniel Dunbar
8c20c162fe
MC/X86: Implement custom lowering to make sure we match things like
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X86::ADC32ri $0, %eax
to
X86::ADC32i32 $0
llvm-svn: 104030
2010-05-18 17:22:24 +00:00
Daniel Dunbar
71107d6099
llc (et al): Add support for --show-encoding and --show-inst.
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llvm-svn: 104029
2010-05-18 17:22:19 +00:00
Dan Gohman
393fa6e0a2
Usage of O_NONBLOCK in bjam is now confirmed as a bug and fixed upstream.
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Update the comment.
llvm-svn: 104021
2010-05-18 15:25:14 +00:00
Benjamin Kramer
ad350eb789
Simplify MCContext::(Next|Get)Instance
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- Allocate MCLabels in the context so they don't leak.
- Avoid duplicated densemap lookup.
llvm-svn: 104020
2010-05-18 12:15:34 +00:00
Alexis Hunt
0774d14741
Replace FIRST_* and LAST_* macros with a generic STMT_RANGE macro
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Also rename ABSTRACT to ABSTRACT_STMT
llvm-svn: 104018
2010-05-18 06:22:50 +00:00
Evan Cheng
39b5115e93
FIX PR7158. SimplifyVBinOp was asserting when it fails to constant fold (op (build_vector), (build_vector)).
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llvm-svn: 104004
2010-05-18 00:03:40 +00:00
Jakob Stoklund Olesen
79b683a9bf
ARMBaseRegisterInfo::estimateRSStackSizeLimit() could return prematurely with a
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too large limit.
The function would return immediately when finding an addrmode 3/5 instruction.
It needs to keep scanning in case there is an addrmode 6 instruction which drops
the limit to 0.
A test case is very difficult to produce because it will only fail when the
scavenger is used.
rdar://problem/7894847
llvm-svn: 103995
2010-05-17 23:29:23 +00:00
Evan Cheng
8aa900cf16
Fix PR7175. Insert copies of a REG_SEQUENCE source if it is used by other REG_SEQUENCE instructions.
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llvm-svn: 103994
2010-05-17 23:24:12 +00:00
Bill Wendling
5a1c9f8d06
- Set the "HasCalls" flag after instruction selection is finished.
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- Change the logic DisableFramePointerElim() to check for the
-disable-non-leaf-fp-elim before -disable-fp-elim.
llvm-svn: 103990
2010-05-17 23:09:50 +00:00