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180 Commits

Author SHA1 Message Date
Jim Grosbach
ef95eee920 Fix ARM encoding of non-return LDM instructions. 
llvm-svn: 118732
 2010-11-10 23:18:49 +00:00
Jim Grosbach
d832c84199 Fix ARM encoding of LDM+Return instruction. 
llvm-svn: 118730
 2010-11-10 23:12:48 +00:00
Bill Wendling
990c247994 Add encoding for VSTR. 
llvm-svn: 118220
 2010-11-04 00:59:42 +00:00
Owen Anderson
f754738bbb Revert r118097 to fix buildbots. 
llvm-svn: 118121
 2010-11-02 23:47:29 +00:00
Owen Anderson
ea89766d0c Since these fields are not exactly equivalent to the encoded field, rename them to something with semantic meaning. 
llvm-svn: 118097
 2010-11-02 22:41:42 +00:00
Owen Anderson
b34a5f1d02 Factor out a common encoding class for loads and stores with a lane parameter. 
llvm-svn: 118055
 2010-11-02 20:47:39 +00:00
Owen Anderson
6647eb222b Add correct NEON encodings for the "multiple single elements" form of vld. 
llvm-svn: 117984
 2010-11-02 00:05:05 +00:00
Bill Wendling
69e7c09c32 Move the machine operand MC encoding patterns to the parent classes. 
llvm-svn: 117956
 2010-11-01 21:17:06 +00:00
Jim Grosbach
53d2661c60 Add 'IsThumb' predicate to patterns marked as 'IsThumb1Only'. The latter gates 
codegen using the patterns; the latter gates the assembler recognizing the
instruction.

llvm-svn: 117931
 2010-11-01 17:08:58 +00:00
Bill Wendling
da3d0ce7b5 Move instruction encoding bits into the parent class and remove the temporary 
*_Encode classes. These instructions are the only ones which use those classes,
so a subclass isn't necessary.

llvm-svn: 117906
 2010-11-01 06:00:39 +00:00
Chris Lattner
a4c36d0efe fix the !eq operator in tblgen to return a bit instead of an int. 
Use this to make the X86 and ARM targets set isCodeGenOnly=1 
automatically for their instructions that have Format=Pseudo,
resolving a hack in tblgen.

llvm-svn: 117862
 2010-10-31 19:22:57 +00:00
Jim Grosbach
996d1280bd Encode the register list operands for ARM mode LDM/STM instructions. 
llvm-svn: 117753
 2010-10-30 00:37:59 +00:00
Jim Grosbach
4ca61d9877 ARM encoding information for CLREX, SWP and SWPB. Add comment for sjlj pseudos and a FIXME for TLS. 
llvm-svn: 117702
 2010-10-29 20:21:36 +00:00
Jim Grosbach
162e3345fb ARM mode LDREX*/STREX* binary encodings. 
llvm-svn: 117695
 2010-10-29 19:58:57 +00:00
Jim Grosbach
86ecfda983 Refactor ARM STR/STRB instruction patterns into STR{B}i12 and STR{B}rs, like 
the LDR instructions have. This makes the literal/register forms of the
instructions explicit and allows us to assign scheduling itineraries
appropriately. rdar://8477752

llvm-svn: 117505
 2010-10-27 23:12:14 +00:00
Owen Anderson
d28d229ded Provide correct encodings for the get_lane and set_lane variants of vmov. 
llvm-svn: 117495
 2010-10-27 21:28:09 +00:00
Owen Anderson
7c46fcfee4 Provide correct NEON encodings for vdup. 
llvm-svn: 117475
 2010-10-27 19:25:54 +00:00
Jim Grosbach
30f6744f05 First part of refactoring ARM addrmode2 (load/store) instructions to be more 
explicit about the operands. Split out the different variants into separate
instructions. This gives us the ability to, among other things, assign
different scheduling itineraries to the variants. rdar://8477752.

llvm-svn: 117409
 2010-10-26 22:37:02 +00:00
Owen Anderson
0cecbd810e Provide correct NEON encodings for vshl, register and immediate forms. 
llvm-svn: 117394
 2010-10-26 20:56:57 +00:00
Owen Anderson
b7618a821f Add NEON encodings for vmov and vmvn of immediates. 
llvm-svn: 117374
 2010-10-26 17:40:54 +00:00
Evan Cheng
59acb7e4cf NEON vmov's are in Neon domain. 
llvm-svn: 117347
 2010-10-26 02:03:05 +00:00
Owen Anderson
59e85cbd66 Add correct instruction encodings for vbic, vorn, and vmvn. 
llvm-svn: 117282
 2010-10-25 18:43:52 +00:00
Owen Anderson
2824342fac Provide correct NEON encodings for vand, veor, and vorr. 
llvm-svn: 117279
 2010-10-25 18:28:30 +00:00
Jim Grosbach
bba77cca02 ARM mode encoding information for CLZ, RBIT, REV*, and PKH*. 
llvm-svn: 117165
 2010-10-22 22:12:16 +00:00
Jim Grosbach
ca2897a0ca More ARM multiply instuction binary encodings. 
llvm-svn: 117121
 2010-10-22 18:35:16 +00:00
Jim Grosbach
eabb7c5bd1 Parameterize a bit of ARM encoding information, simplifying some instruction 
definitions.

llvm-svn: 117114
 2010-10-22 17:42:06 +00:00
Jim Grosbach
0ae6bf8095 More ARM multiply instruction encoding information. 
llvm-svn: 117108
 2010-10-22 17:16:17 +00:00
Owen Anderson
ba2ac80921 ARM encodes Q registers as 2xregno (i.e. the number of the D register that corresponds to the lower 
half of the Q register), rather than with just regno.  This allows us to unify the encodings for
a lot of different NEON instrucitons that differ only in whether they have Q or D register operands.

llvm-svn: 117056
 2010-10-21 20:21:49 +00:00
Bob Wilson
fcc42f2f3a ARM instructions that are both predicated and set the condition codes 
have been printed with the "S" modifier after the predicate.  With ARM's
unified syntax, they are supposed to go in the other order.  We fixed this
for Thumb when we switched to unified syntax but missed changing it for
ARM.  Apparently we don't generate these instructions often because no one
noticed until now.  Thanks to Bill Wendling for the testcase!

llvm-svn: 116563
 2010-10-15 03:23:44 +00:00
Jim Grosbach
2e8a589fb2 trailing whitespace 
llvm-svn: 116450
 2010-10-13 23:12:26 +00:00
Jim Grosbach
1699d40f80 Refactor the ARM 'setend' instruction pattern. Use a single instruction pattern 
and handle the operand explicitly. Flesh out encoding information. Add an
explicit disassembler testcase for the instruction.

llvm-svn: 116432
 2010-10-13 21:00:04 +00:00
Jim Grosbach
8f0bea85bf Add ARM mode encoding for [SU]XT[BH] and [SU]XTA[BH] instructions. 
llvm-svn: 116421
 2010-10-13 19:56:10 +00:00
Jim Grosbach
f4cf5bef46 Add custom encoder for the 's' bit denoting whether an ARM arithmetic 
instruction should set the processor status flags or not. Remove the now
unnecessary special handling for the bit from the MCCodeEmitter.

llvm-svn: 116360
 2010-10-12 23:00:24 +00:00
Bill Wendling
79d57782ad Split out the "size" field from the encoding. The newer documentation has it as 
a separate bit in the coding.

llvm-svn: 116347
 2010-10-12 22:03:19 +00:00
Jim Grosbach
58ee6f3972 Encoding for ARM-mode VADD.F32 instruction. 
llvm-svn: 116338
 2010-10-12 21:22:40 +00:00
Jim Grosbach
a697e32f36 More binary encoding stuff, taking advantage of the new "by name" operand 
matching in tblgen to do the predicate operand.

llvm-svn: 116213
 2010-10-11 18:51:51 +00:00
Jim Grosbach
54490de165 Add a 'pattern' arg to the ARM PseudoNeonI class. 
llvm-svn: 115831
 2010-10-06 20:36:55 +00:00
Chris Lattner
0b644ced02 replace stuff like: 
let AsmString = !strconcat(
                     !strconcat(!strconcat(opc, "${p}"), !strconcat(".", dt)),
                     !strconcat("\t", asm));

with:

  let AsmString = !strconcat(opc, "${p}", ".", dt, "\t", asm);

:)

llvm-svn: 115720
 2010-10-06 00:05:18 +00:00
Jim Grosbach
7c112a9c65 Increase the number of bits used internally by the ARM target to represent the 
addressing mode from four to five.

llvm-svn: 115645
 2010-10-05 18:14:55 +00:00
Bob Wilson
c63e8b4d2d Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded after 
register allocation to VLDMD and VSTMD respectively.  This avoids using the
dregpair operand modifier.

llvm-svn: 114047
 2010-09-16 00:31:02 +00:00
Bob Wilson
ba02d5b620 Convert some VTBL and VTBX instructions to use pseudo instructions prior to 
register allocation.  Remove the NEONPreAllocPass, which is no longer needed.
Yeah!!

llvm-svn: 113818
 2010-09-13 23:55:10 +00:00
Jim Grosbach
27a5b1fd3b VFP/NEON load/store multiple instructions are addrmode4, not 5. 
llvm-svn: 113322
 2010-09-08 00:25:50 +00:00
Bill Wendling
0409e77e99 - Cleanup some whitespaces. 
- Convert {0,1} and friends into 0b01, which is identical and more consistent.

llvm-svn: 112593
 2010-08-31 07:50:46 +00:00
Bill Wendling
7532e3418e Use the existing T2I_bin_s_irs pattern instead of creating T2I_bin_sw_irs, which 
is meant to do exactly the same thing. Thanks to Jim Grosbach for pointing this
out! :-)

llvm-svn: 112538
 2010-08-30 22:05:23 +00:00
Bill Wendling
c325a15569 Create Thumb2sI_cpsr and T2sI_cpsr. These new classes indicate that CPSR is the 
optional modified register (instead of reg0). Along with r112461 it will make
sure that the optional define of CPSR is marked as "def" and will thus mark the
instructions using these classes (t2ANDS*) as setting the 's' flag.

llvm-svn: 112462
 2010-08-30 01:47:35 +00:00
Bob Wilson
b85b3cf91f Start converting NEON load/stores to use pseudo instructions, beginning here 
with the VST4 instructions.  Until after register allocation, we want to
represent sets of adjacent registers by a single super-register.  These
VST4 pseudo instructions have a single QQ or QQQQ source register operand.
They get expanded to the real VST4 instructions with 4 separate D register
operands.  Once this conversion is complete, we'll be able to remove the
NEONPreAllocPass and avoid some fragile and hacky code elsewhere.

llvm-svn: 112108
 2010-08-25 23:27:42 +00:00
Daniel Dunbar
74ed9321a3 MC/ARM: Add an ARMOperand class for condition codes. 
llvm-svn: 110788
 2010-08-11 06:36:53 +00:00
Bob Wilson
0650cceb38 Add a separate ARM instruction format for Saturate instructions. 
(I discovered 2 more copies of the ARM instruction format list, bringing the
total to 4!!  Two of them were already out of sync.  I haven't yet gotten into
the disassembler enough to know the best way to fix this, but something needs
to be done.)  Add support for encoding these instructions.

llvm-svn: 110754
 2010-08-11 00:01:18 +00:00
Xerxes Ranby
c7a04bcaa5 ARMv4 JIT forgets to set the lr register when making a indirect function call. Fixes PR7608 
llvm-svn: 109125
 2010-07-22 17:28:34 +00:00
Bob Wilson
a3b10d15f2 Renumber NEON instruction formats to be consecutive. 
llvm-svn: 106927
 2010-06-26 00:05:09 +00:00