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908 Commits

Author SHA1 Message Date
Matt Arsenault
9e400b2e26 R600/SI: Match rsq instructions 
llvm-svn: 210226
 2014-06-05 00:15:55 +00:00
Matt Arsenault
d9ef70c461 Use nullptr 
llvm-svn: 210222
 2014-06-05 00:01:12 +00:00
Matt Arsenault
ad098591b8 Fix typos 
llvm-svn: 210135
 2014-06-03 23:06:13 +00:00
Matt Arsenault
a36a2916ac R600: Set all float vector expands in the same place 
llvm-svn: 209988
 2014-06-01 07:38:21 +00:00
Matt Arsenault
1c23cf5566 R600/SI: Remove redundant patterns 
These patterns are already handled in the instruction definition.

llvm-svn: 209979
 2014-05-31 19:25:17 +00:00
Matt Arsenault
ff3cea9ab5 R600/SI: Fix [s|u]int_to_fp for i1 
llvm-svn: 209971
 2014-05-31 06:47:42 +00:00
Matt Arsenault
0f46ee15d3 R600/SI: Fix pattern variable names. 
These are confusing enough since the order swaps,
so give them more useful names.

llvm-svn: 209787
 2014-05-29 01:18:01 +00:00
Matt Arsenault
7d507483f4 R600: Add definition for flat address space ID. 
Use 4 since that's probably what it will be for spir.
Move ADDRESS_NONE to the end to keep the constant_buffer_* values
unchanged, since apparently a bunch of r600 tests use those directly.

llvm-svn: 209463
 2014-05-22 18:27:07 +00:00
Matt Arsenault
bfc007dbb5 R600: Try to convert BFE back to standard bit ops when possible. 
This allows existing DAG combines to work on them, and then
we can re-match to BFE if necessary during instruction selection.

llvm-svn: 209462
 2014-05-22 18:09:12 +00:00
Matt Arsenault
90d0fd2ea0 R600: Add dag combine for BFE 
llvm-svn: 209461
 2014-05-22 18:09:07 +00:00
Matt Arsenault
4ab9246e99 R600: Implement ComputeNumSignBitsForTargetNode for BFE 
llvm-svn: 209460
 2014-05-22 18:09:03 +00:00
Matt Arsenault
3728da5d51 R600: Implement computeMaskedBitsForTargetNode for BFE 
llvm-svn: 209459
 2014-05-22 18:09:00 +00:00
Matt Arsenault
c7d0679684 R600: Expand mul24 for GPUs without it 
llvm-svn: 209458
 2014-05-22 18:00:24 +00:00
Matt Arsenault
fcb6cf68ee R600: Expand mad24 for GPUs without it 
llvm-svn: 209457
 2014-05-22 18:00:20 +00:00
Matt Arsenault
e43426533f R600: Add intrinsics for mad24 
llvm-svn: 209456
 2014-05-22 18:00:15 +00:00
Matt Arsenault
8c8ff09456 R600/SI: Move instruction pattern to instruction definition 
llvm-svn: 209454
 2014-05-22 17:45:20 +00:00
Matt Arsenault
cec6ae49e8 R600/SI: Match fp_to_uint / uint_to_fp for f64 
llvm-svn: 209388
 2014-05-22 03:20:30 +00:00
Matt Arsenault
8ec42a3269 R600: Add comment describing problems with LowerConstantInitializer 
llvm-svn: 209333
 2014-05-21 22:59:17 +00:00
Matt Arsenault
094f9f1e9c R600: Partially fix constant initializers for structs and vectors. 
This should extend the current workaround to work with structs
that only contain legal, scalar types.

llvm-svn: 209331
 2014-05-21 22:42:42 +00:00
Matt Arsenault
90ef7a5eaa Use cast<> instead of unchecked dyn_cast 
llvm-svn: 209310
 2014-05-21 18:03:59 +00:00
Matt Arsenault
cb883e1e39 Remove unused method declaration 
llvm-svn: 209174
 2014-05-19 22:55:35 +00:00
Aaron Ballman
f2386ff79f Resolving MSVC warnings about switch statements with a default label, but no case labels. No functional changes intended. 
llvm-svn: 209126
 2014-05-19 14:29:04 +00:00
Tom Stellard
a6f7eff1ad R600/SI: Refactor the VOP3_32 tablegen class 
This will allow us to use a single MachineInstr to represent
instructions which behave the same but have different encodings
on some subtargets.

llvm-svn: 209028
 2014-05-16 20:56:47 +00:00
Tom Stellard
724f41cd91 R600/SI: Add a PredicateControl class for managing TableGen predicates 
This was inspired by the PredicateControl class in the MIPS backend.

llvm-svn: 209027
 2014-05-16 20:56:45 +00:00
Tom Stellard
dd51c2b7f4 R600/SI: Move tablegen patterns away from instruction defs 
llvm-svn: 209026
 2014-05-16 20:56:44 +00:00
Tom Stellard
caa7274fef R600/SI: Remove unused instruction 
llvm-svn: 209025
 2014-05-16 20:56:43 +00:00
Tom Stellard
2022c1eb1b R600/SI: Promote f32 SELECT to i32 
llvm-svn: 209024
 2014-05-16 20:56:41 +00:00
Tom Stellard
9ed79b238d R600/SI: Remove duplicate pattern 
llvm-svn: 209023
 2014-05-16 20:56:37 +00:00
Matt Arsenault
6a9e6f69e7 Use range for 
llvm-svn: 208922
 2014-05-15 21:44:05 +00:00
Tom Stellard
dbf9b9b7af R600/SI: Stop using VSrc_* as the default register class for types. 
We now use SReg_* for integer types and VReg_* for floating-point types.
This should help simplify the SIFixSGPRCopies pass and no longer causes
ISel to insert a COPY after termiator instuctions that output a value.

This change is covered by exisitng tests.

llvm-svn: 208888
 2014-05-15 14:41:57 +00:00
Tom Stellard
d01bb8adfa R600/SI: Fix a bug with handling of INSERT_SUBREG in SIFixSGPRCopies 
This prevents a future commit from regressing the load-i1.ll test.

llvm-svn: 208887
 2014-05-15 14:41:55 +00:00
Tom Stellard
77051e93a5 R600/SI: Only use SALU instructions for 64-bit add in a block of CF depth 0 
llvm-svn: 208886
 2014-05-15 14:41:54 +00:00
Tom Stellard
efb8470c62 R600/SI: Use VALU instructions for i1 ops 
llvm-svn: 208885
 2014-05-15 14:41:50 +00:00
Jay Foad
e0eac700cb Rename ComputeMaskedBits to computeKnownBits. "Masked" has been 
inappropriate since it lost its Mask parameter in r154011.

llvm-svn: 208811
 2014-05-14 21:14:37 +00:00
Matt Arsenault
102b7be363 R600/SI: Try to fix BFE operands when moving to VALU 
This was broken by r208479

llvm-svn: 208740
 2014-05-13 23:45:50 +00:00
Matt Arsenault
7739d11cce Use cast<> for unchecked use 
llvm-svn: 208627
 2014-05-12 20:42:57 +00:00
Matt Arsenault
aa6b8c3524 Use cast<> for unchecked use 
llvm-svn: 208618
 2014-05-12 19:26:38 +00:00
Matt Arsenault
133f79f1a6 Use range for 
llvm-svn: 208617
 2014-05-12 19:23:21 +00:00
Matt Arsenault
c2251d492b R600: Add mul24 intrinsics 
llvm-svn: 208604
 2014-05-12 17:49:57 +00:00
Matt Arsenault
8358bf5227 Fix return before else 
llvm-svn: 208510
 2014-05-11 21:24:41 +00:00
Vincent Lejeune
03352d8b38 R600/SI: Fold fabs/fneg into src input modifier 
llvm-svn: 208480
 2014-05-10 19:18:39 +00:00
Vincent Lejeune
840594f1e6 R600/SI: Prettier display of input modifiers 
llvm-svn: 208479
 2014-05-10 19:18:33 +00:00
Vincent Lejeune
8467918b43 R600/SI: Use pseudo instruction for fabs/clamp/fneg 
llvm-svn: 208478
 2014-05-10 19:18:25 +00:00
Tom Stellard
1a986ede50 R600/SI: Teach SIInstrInfo::moveToVALU() how to move S_LOAD_*_IMM instructions 
llvm-svn: 208432
 2014-05-09 16:42:22 +00:00
Tom Stellard
550d79da42 R600/SI: Fix SMRD pattern for offsets > 32 bits 
We were dropping the high bits of 64-bit immediate offsets.

llvm-svn: 208431
 2014-05-09 16:42:21 +00:00
Tom Stellard
9562e8a6ba R600: Expand i64 SELECT_CC 
llvm-svn: 208430
 2014-05-09 16:42:19 +00:00
Tom Stellard
83d3208148 R600: Move MIN/MAX matching from LowerOperation() to PerformDAGCombine() 
llvm-svn: 208429
 2014-05-09 16:42:16 +00:00
Matt Arsenault
119209fcfe R600: Promote f64 vector load/stores to i64 for consistency 
llvm-svn: 208344
 2014-05-08 18:01:56 +00:00
Tom Stellard
1291d8f8c2 R600: Expand i64 ISD:SUB 
llvm-svn: 208005
 2014-05-05 21:47:15 +00:00
Marek Olsak
6fa0778eff R600/SI: allow 5 more input SGPRs to a shader 
Our OpenGL driver needs 22 SGPRs (16 user SGPRs + 6 streamout non-user SGPRs).

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
llvm-svn: 207990
 2014-05-05 19:30:54 +00:00