Akira Hatanaka
03b00bdf4d
Remove aligned/unaligned load/store fragments defined in MipsInstrInfo.td and
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use load/store fragments defined in TargetSelectionDAG.td in place of them.
Unaligned loads/stores are either expanded or lowered to target-specific nodes,
so instruction selection should see only aligned load/store nodes.
No changes in functionality.
llvm-svn: 163960
2012-09-15 01:52:08 +00:00
Akira Hatanaka
4e1b032521
Add stub methods for mips assembly matcher.
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Patch by Vladimir Medic.
llvm-svn: 162124
2012-08-17 20:16:42 +00:00
Akira Hatanaka
e1beddb7e8
Define ADJCALLSTACKDOWN/UP nodes. These nodes are emitted regardless of whether
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or not it is in mips16 mode. Define MipsPseudo (mode-independant pseudo) and
PseudoSE (mips32/64 pseudo) classes.
llvm-svn: 161071
2012-07-31 19:13:07 +00:00
Akira Hatanaka
aab47c049b
Fix type of LUXC1 and SUXC1. These instructions were incorrectly defined as
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single-precision load and store.
Also avoid selecting LUXC1 and SUXC1 instructions during isel. It is incorrect
to map unaligned floating point load/store nodes to these instructions.
llvm-svn: 161063
2012-07-31 18:16:49 +00:00
Akira Hatanaka
d1b2b96ed5
1. introduce MipsPat in place of Pat in order to exclude those from
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being used by Mips16 or Micro Mips
2. clean up a few lines too long encountered
Patch by Reed Kotler.
llvm-svn: 158470
2012-06-14 21:03:23 +00:00
Akira Hatanaka
2a600ff5f4
This patch adds a predicate to existing mips32 and mips64 so that those
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instruction encodings can be excluded during mips16 processing.
This revision fixes the issue raised by Jim Grosbach.
bool hasStandardEncoding() const { return !inMips16Mode(); }
When micromips is added it will be
bool StandardEncoding() const { return !inMips16Mode()&& !inMicroMipsMode(); }
No additional testing is needed other than to assure that there is no regression
from this patch.
Patch by Reed Kotler.
llvm-svn: 157234
2012-05-22 03:10:09 +00:00
Akira Hatanaka
ecb1cd1ce4
Add disassembler to MIPS.
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Patch by Vladimir Medic.
llvm-svn: 154935
2012-04-17 18:03:21 +00:00
Akira Hatanaka
48dbb62cb1
Emit neg.s or neg.d only if -enable-no-nans-fp-math is supplied by user,
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otherwise expand FNEG during legalization.
llvm-svn: 154546
2012-04-11 22:59:08 +00:00
Akira Hatanaka
11a442d515
Emit abs.s or abs.d only if -enable-no-nans-fp-math is supplied by user.
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Invalid operation is signaled if the operand of these instructions is NaN.
llvm-svn: 154545
2012-04-11 22:49:04 +00:00
Akira Hatanaka
cecb440c11
Revert r153924. There were buildbot failures.
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llvm-svn: 153925
2012-04-03 02:51:09 +00:00
Akira Hatanaka
058b0cfb55
MIPS disassembler support.
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Patch by Vladimir Medic.
llvm-svn: 153924
2012-04-03 02:20:58 +00:00
Akira Hatanaka
75b06f4a49
Fix bugs which were introduced when support for base+index floating point loads
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and stores was added.
- SelectAddr should return false if Parent is an unaligned f32 load or store.
- Only aligned load and store nodes should be matched to select reg+imm
floating point instructions.
- MIPS does not have support for f64 unaligned load or store instructions.
llvm-svn: 151843
2012-03-01 22:12:30 +00:00
Jia Liu
bdcd314be3
remove blanks, and some code format
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llvm-svn: 151625
2012-02-28 07:46:26 +00:00
Akira Hatanaka
0934449dd8
Add support for floating point base register + offset register addressing mode
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load and store instructions.
llvm-svn: 151611
2012-02-28 02:55:02 +00:00
Akira Hatanaka
28521d25c9
Remove unnecessary template parameters.
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llvm-svn: 151540
2012-02-27 19:17:53 +00:00
Akira Hatanaka
1e3ba02d8d
Fix instruction predicates that were not set correctly.
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llvm-svn: 151538
2012-02-27 19:09:08 +00:00
Akira Hatanaka
8fc9a35d3f
Add definitions of floating point multiply add/sub and negative multiply
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add/sub instructions.
llvm-svn: 151415
2012-02-25 00:21:52 +00:00
Akira Hatanaka
1593eafa1e
Remove trailing whitespace. Add newline.
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llvm-svn: 150706
2012-02-16 17:48:20 +00:00
Akira Hatanaka
12cdcf3bc6
Pattern for f32 to i64 conversion.
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llvm-svn: 148869
2012-01-24 22:05:25 +00:00
Akira Hatanaka
36db890397
Various Mips64 floating point instruction patterns.
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llvm-svn: 144019
2011-11-07 21:38:58 +00:00
Akira Hatanaka
cc6491001f
Add definition of the base class for floating point comparison instructions
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and add Mips64's version too.
llvm-svn: 144018
2011-11-07 21:37:33 +00:00
Akira Hatanaka
db8cbab444
Add definitions of 64-bit instructions which move data between integer and
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floating pointer registers.
llvm-svn: 144016
2011-11-07 21:32:58 +00:00
Bruno Cardoso Lopes
edc2e30d42
Final patch that completes old JIT support for Mips:
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-Fix binary codes and rename operands in .td files so that automatically
generated function MipsCodeEmitter::getBinaryCodeForInstr gives correct
encoding for instructions.
-Define new class FMem for instructions that access memory.
-Define new class FFRGPR for instructions that move data between GPR and
FPU general and control registers.
-Define custom encoder methods for memory operands, and also for size
operands of ext and ins instructions.
-Only static relocation model is currently implemented.
Patch by Sasa Stankovic
llvm-svn: 142378
2011-10-18 17:50:36 +00:00
Akira Hatanaka
e8cb50da87
Move class and instruction definitions for conditional moves to a seperate file.
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llvm-svn: 142220
2011-10-17 18:43:19 +00:00
Akira Hatanaka
20808df5a0
Make changes necessary for supporting floating point load and store instructions
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that have 64-bit pointers or access the 32 x 64-bit floating pointer register
file. Update functions in MipsInstrInfo.cpp too.
llvm-svn: 141623
2011-10-11 01:12:52 +00:00
Akira Hatanaka
4a78bb776f
Simplify definition of FP move instructions.
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llvm-svn: 141476
2011-10-08 03:50:18 +00:00
Akira Hatanaka
7780dcc74e
Define classes and multiclasses for FP binary instructions.
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llvm-svn: 141475
2011-10-08 03:38:41 +00:00
Akira Hatanaka
9595e84a11
Define multiclasses for FP-to-FP instructions.
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llvm-svn: 141474
2011-10-08 03:29:22 +00:00
Akira Hatanaka
e39c39db4a
Define classes for FP unary instructions and multiclasses for FP-to-fixed point
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conversion instructions.
llvm-svn: 141473
2011-10-08 03:19:38 +00:00
Jakob Stoklund Olesen
6cb1647b24
Revert r140731, "Define classes for unary and binary FP instructions and use them to define"
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It broke the unit tests. Please reapply with tests fixed.
llvm-svn: 140735
2011-09-28 23:59:28 +00:00
Akira Hatanaka
be2c5236ec
Define classes for unary and binary FP instructions and use them to define
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multiclasses.
llvm-svn: 140731
2011-09-28 21:58:01 +00:00
Akira Hatanaka
0510b9d75b
Rename predicate In32BitMode to NotFP64bit and add definition of IsFP64bit.
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llvm-svn: 140705
2011-09-28 18:11:19 +00:00
Akira Hatanaka
fa83d9ff16
Remove definitions of branch-on-FP-likely instructions. They are deprecated.
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llvm-svn: 140704
2011-09-28 17:56:55 +00:00
Akira Hatanaka
ea4d87c3e8
Remove MipsFPRound. Mips1 is no longer supported.
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llvm-svn: 140661
2011-09-27 23:55:37 +00:00
Akira Hatanaka
d44d75eccf
Embed patterns in definitions of MFC1 and MTC1 instead of defining them outside
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of the instruction definitions using Pat<>.
llvm-svn: 140644
2011-09-27 22:01:01 +00:00
Akira Hatanaka
c83a0bb4b6
Make changes in instruction and pattern definitions so that tablegen does not
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complain it cannot infer types in patterns. Fix a mistake in definition of
SDT_MipsExtractElementF64.
llvm-svn: 140354
2011-09-22 23:31:54 +00:00
Akira Hatanaka
f65d050693
Drop support for Mips1 and Mips2.
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llvm-svn: 139405
2011-09-09 20:45:50 +00:00
Akira Hatanaka
12df91513e
Fix handling of double precision loads and stores when Mips1 is targeted.
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Mips1 does not support double precision loads or stores, therefore two single
precision loads or stores must be used in place of these instructions. This
patch treats double precision loads and stores as if they are legal
instructions until MCInstLowering, instead of generating the single precision
instructions during instruction selection or Prolog/Epilog code insertion.
Without the changes made in this patch, llc produces code that has the same
problem described in r137484 or bails out when
MipsInstrInfo::storeRegToStackSlot or loadRegFromStackSlot is called before
register allocation.
llvm-svn: 137711
2011-08-16 03:51:51 +00:00
Akira Hatanaka
f56f544d80
Use tabs to separate opcode and operand strings.
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llvm-svn: 132718
2011-06-07 18:16:51 +00:00
Akira Hatanaka
5b696387f7
Add pattern for double-to-integer conversion. Patch by Sasa Stankovic.
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llvm-svn: 131927
2011-05-23 22:16:43 +00:00
Akira Hatanaka
a57b77b65f
Fix setting of isCommutable flag.
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llvm-svn: 131233
2011-05-12 17:42:08 +00:00
Eric Christopher
49409b8534
Fix td file comments for Mips.
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Patch by Liu <proljc@gmail.com>!
llvm-svn: 131086
2011-05-09 18:16:46 +00:00
Akira Hatanaka
74d45b54f1
Reverse unnecessary changes made in r129606 and r129608. There is no change in functionality.
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llvm-svn: 129612
2011-04-15 21:51:11 +00:00
Akira Hatanaka
6f900185ed
Fix lines that have incorrect indentation or exceed 80 columns. There is no change in functionality.
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llvm-svn: 129606
2011-04-15 21:00:26 +00:00
Akira Hatanaka
025720d06f
Add pass that expands pseudo instructions into target instructions after register allocation. Define pseudos that get expanded into mtc1 or mfc1 instructions.
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llvm-svn: 129594
2011-04-15 19:52:08 +00:00
Chris Lattner
0304b82f80
Fix a ton of comment typos found by codespell. Patch by
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Luis Felipe Strano Moraes!
llvm-svn: 129558
2011-04-15 05:18:47 +00:00
Akira Hatanaka
b26c89ee68
Added support for FP conditional move instructions and fixed bugs in handling of FP comparisons.
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llvm-svn: 128650
2011-03-31 18:26:17 +00:00
Bruno Cardoso Lopes
5400401372
Remove (hopefully) all trailing whitespaces from the mips backend. Patch by Hatanaka, Akira
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llvm-svn: 127003
2011-03-04 17:51:39 +00:00
Chris Lattner
01e8c46349
Flag -> Glue, the ongoing saga
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llvm-svn: 122513
2010-12-23 18:28:41 +00:00
Chris Lattner
a556264e06
fix emacs language spec's, patch by Edmund Grimley-Evans!
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llvm-svn: 111241
2010-08-17 16:20:04 +00:00