Make sure TernOpInits are unique and created only once. This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.
llvm-svn: 136496
Make sure BinOpInits are unique and created only once. This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.
llvm-svn: 136495
Make sure UnOpInits are unique and created only once. This will be
important for AVX/SIMD as many operators will be used to generate
patterns and other relevant data.
llvm-svn: 136494
Ensure ListInits are unique and only created once. This will be
important for AVX as lists will be used extensively to pass generic
patterns, prefix information and other things to lower-level
pattern-generation classes.
llvm-svn: 136493
Use a StringMap to ensure the StringInits are unique. This is
especially important for AVX where we will have many smallish
strings representing instruction prefixes, suffixes and the like.
llvm-svn: 136491
Remove all non-const iterators from Init classes. This is another
step toward constifying Inits and ultimately turning them into
FoldingSetNodes.
llvm-svn: 136484
Create a std::string wrapper for use as a DenseMap key. DenseMap is
not safe in generate with strings, so this wrapper indicates that only
strings guaranteed not to have certain values should be used in the
DenseMap.
llvm-svn: 136481
This can happen in cases where TableGen generated asm matcher cannot check
whether a register operand is in the right register class. e.g. mem operands.
rdar://8204588
llvm-svn: 136292
llvm-mc gives an "invalid operand" error for instructions that take an unsigned
immediate which have the high bit set such as:
pblendw $0xc5, %xmm2, %xmm1
llvm-mc treats all x86 immediates as signed values and range checks them.
A small number of x86 instructions use the imm8 field as a set of bits.
This change only changes those instructions and where the high bit is not
ignored. The others remain unchanged.
llvm-svn: 136287
This makes TargetRegisterClass slightly slower. Next step will be making contains faster.
Eventually TargetRegisterClass will be killed entirely.
llvm-svn: 135835
The immediate is in the range 1-32, but is encoded as 0-31 in a 5-bit bitfield.
Update the representation such that we store the operand as 0-31, allowing us
to remove the encoder method and the special case handling in the disassembler.
Update the assembly parser and the instruction printer accordingly.
llvm-svn: 135823
Move the shift operator and special value (32 encoded as 0 for PKHTB) handling
into the instruction printer. This cleans up a bit of the disassembler
special casing for these instructions, more easily handles not printing the
operand at all for "lsl #0" and prepares for correct asm parsing of these
operands.
llvm-svn: 135626
