Craig Topper
6fb0648c41
Add XOP disassembler support. Fixes PR13933.
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llvm-svn: 191874
2013-10-03 05:17:48 +00:00
Craig Topper
13fe261777
Add a few more FMA4 disassembler test cases to match the scalar set with regards to combinations of L and W-bits.
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llvm-svn: 191650
2013-09-30 02:50:51 +00:00
Craig Topper
a4bd7d9c3c
Various x86 disassembler fixes.
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Add VEX_LIG to scalar FMA4 instructions.
Use VEX_LIG in some of the inheriting checks in disassembler table generator.
Make use of VEX_L_W, VEX_L_W_XS, VEX_L_W_XD contexts.
Don't let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from their non-L forms unless VEX_LIG is set.
Let VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE inherit from all of their non-L or non-W cases.
Increase ranking on VEX_L_W, VEX_L_W_XS, VEX_L_W_XD, VEX_L_W_OPSIZE so they get chosen over non-L/non-W forms.
llvm-svn: 191649
2013-09-30 02:46:36 +00:00
Craig Topper
c7bcbfdf42
Don't let x86 asm printer use the no operand movsd alias. It should use the normal movsl instead.
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llvm-svn: 186924
2013-07-23 01:50:47 +00:00
Kevin Enderby
b71a2e2f2e
Update the X86 disassembler to use xacquire and xrelease when appropriate.
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This is a bit tricky as the xacquire and xrelease hints use the same bytes,
0xf2 and 0xf3, as the repne and rep prefixes.
Fortunately llvm has different llvm MCInst Opcode enums for rep/xrelease
and repne/xacquire. So to make this work a boolean was added the
InternalInstruction struct as part of the Prefix state which is set with the
added logic in readPrefixes() when decoding an instruction to determine
if these prefix bytes are to be disassembled as xacquire or xrelease. Then
we let the matcher pick the normal prefix instructionID and we change the
Opcode after that when it is set into the MCInst being created.
rdar://11019859
llvm-svn: 184490
2013-06-20 22:32:18 +00:00
Dave Zarzycki
b443618b88
x86 -- disassemble the REP/REPNE prefix when needed
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This fixes Apple bug: 13493622
llvm-svn: 177887
2013-03-25 18:59:38 +00:00
Craig Topper
7af95b6c84
Fix suffix handling for parsing and printing of cvtsi2ss, cvtsi2sd, cvtss2si, cvttss2si, cvtsd2si, and cvttsd2si to match gas behavior.
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cvtsi2* should parse with an 'l' or 'q' suffix or no suffix at all. No suffix should be treated the same as 'l' suffix. Printing should always print a suffix. Previously we didn't parse or print an 'l' suffix.
cvtt*2si/cvt*2si should parse with an 'l' or 'q' suffix or not suffix at all. No suffix should use the destination register size to choose encoding. Printing should not print a suffix.
Original 'l' suffix issue with cvtsi2* pointed out by Michael Kuperstein.
llvm-svn: 171668
2013-01-06 20:39:29 +00:00
Craig Topper
9667d599eb
Make l/q suffixes on AVX forms of scalar convert instructions consistent with their non-AVX forms.
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llvm-svn: 160775
2012-07-26 07:48:28 +00:00
Craig Topper
b346ce8240
Reverse assembler/disassembler operand order for gather instructions.
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llvm-svn: 159983
2012-07-10 06:38:33 +00:00
Manman Ren
63bf58865a
X86: add more GATHER intrinsics in LLVM
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Corrected type for index of llvm.x86.avx2.gather.d.pd.256
from 256-bit to 128-bit.
Corrected types for src|dst|mask of llvm.x86.avx2.gather.q.ps.256
from 256-bit to 128-bit.
Support the following intrinsics:
llvm.x86.avx2.gather.d.q, llvm.x86.avx2.gather.q.q
llvm.x86.avx2.gather.d.q.256, llvm.x86.avx2.gather.q.q.256
llvm.x86.avx2.gather.d.d, llvm.x86.avx2.gather.q.d
llvm.x86.avx2.gather.d.d.256, llvm.x86.avx2.gather.q.d.256
llvm-svn: 159402
2012-06-29 00:54:20 +00:00
Manman Ren
6be46b7b4c
X86: add GATHER intrinsics (AVX2) in LLVM
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Support the following intrinsics:
llvm.x86.avx2.gather.d.pd, llvm.x86.avx2.gather.q.pd
llvm.x86.avx2.gather.d.pd.256, llvm.x86.avx2.gather.q.pd.256
llvm.x86.avx2.gather.d.ps, llvm.x86.avx2.gather.q.ps
llvm.x86.avx2.gather.d.ps.256, llvm.x86.avx2.gather.q.ps.256
Modified Disassembler to handle VSIB addressing mode.
llvm-svn: 159221
2012-06-26 19:47:59 +00:00
Kevin Enderby
8afd951f49
Change the second line of the test added for r152414 to use CHECK-NEXT.
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Suggestion by Bill Wendling!
llvm-svn: 152582
2012-03-12 21:38:09 +00:00
Kevin Enderby
1a3b6570f8
Fix the x86 disassembler to at least print the lock prefix if it is the first
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prefix. Added a FIXME to remind us this still does not work when it is not the
first prefix.
llvm-svn: 152414
2012-03-09 17:52:49 +00:00
Craig Topper
ab46706aa9
X86 disassembler support for jcxz, jecxz, and jrcxz. Fixes PR11643. Patch by Kay Tiong Khoo.
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llvm-svn: 151510
2012-02-27 01:54:29 +00:00
Craig Topper
cfbfa3dcd1
Add vmfunc instruction to X86 assembler and disassembler.
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llvm-svn: 150899
2012-02-19 01:39:49 +00:00
Craig Topper
ecf21d8132
Add X86 assembler and disassembler support for AMD SVM instructions. Original patch by Kay Tiong Khoo. Few tweaks by me for code density and to reduce replication.
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llvm-svn: 150873
2012-02-18 08:19:49 +00:00
Craig Topper
b4db8689ee
Add disassembler support for VPERMIL2PD and VPERMIL2PS.
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llvm-svn: 147368
2011-12-30 06:23:39 +00:00
Craig Topper
089be4fefa
Add FMA4 instructions to disassembler.
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llvm-svn: 147367
2011-12-30 05:20:36 +00:00
Craig Topper
97e84c23a1
Fix execution domains for PS/PD FMA3 instructions. Add SS/SD forms o FMA3 instructions.
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llvm-svn: 147353
2011-12-29 20:43:40 +00:00
Craig Topper
bcfd070378
Expose FMA3 instructions to the disassembler.
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llvm-svn: 147351
2011-12-29 20:03:14 +00:00
Craig Topper
3cb62dca0f
Add X86 SARX, SHRX, and SHLX instructions.
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llvm-svn: 142779
2011-10-23 22:18:24 +00:00
Craig Topper
0e63b4485c
Add X86 RORX instruction
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llvm-svn: 142741
2011-10-23 07:34:00 +00:00
Craig Topper
7019cf1b80
Add X86 MULX instruction for disassembler.
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llvm-svn: 142738
2011-10-23 00:33:32 +00:00
Craig Topper
b1fa647871
Rename PEXTR to PEXT. Add intrinsics for BMI instructions.
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llvm-svn: 142480
2011-10-19 07:48:35 +00:00
Craig Topper
6c900d9810
Add X86 PEXTR and PDEP instructions.
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llvm-svn: 142141
2011-10-16 16:50:08 +00:00
Craig Topper
2cd868184c
Add X86 BZHI instruction as well as BMI2 feature detection.
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llvm-svn: 142122
2011-10-16 07:55:05 +00:00
Craig Topper
91b4292682
Add X86 INVPCID instruction. Add 32/64-bit predicates to INVEPT, INVVPID, VMREAD, and VMWRITE to remove hack from X86RecognizableInstr.
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llvm-svn: 142117
2011-10-16 07:05:40 +00:00
Craig Topper
4c6357d4af
Add X86 BEXTR instruction. This instruction uses VEX.vvvv to encode Operand 3 instead of Operand 2 so needs special casing in the disassembler and code emitter. Ultimately, should pass this information from tablegen
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llvm-svn: 142105
2011-10-16 03:51:13 +00:00
Craig Topper
62e63d9bb9
Add support for X86 blsr, blsmsk, and blsi instructions. Required extra work because these are the first VEX encoded instructions to use the reg field as an opcode extension.
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llvm-svn: 142082
2011-10-15 20:46:47 +00:00
Craig Topper
0a11eb1b21
Add X86 ANDN instruction. Including instruction selection.
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llvm-svn: 141947
2011-10-14 07:06:56 +00:00
Craig Topper
6b2120a8e1
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141939
2011-10-14 03:21:46 +00:00
Bill Wendling
2a571af745
Revert r141854 because it was causing failures:
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http://lab.llvm.org:8011/builders/llvm-x86_64-linux/builds/101
--- Reverse-merging r141854 into '.':
U test/MC/Disassembler/X86/x86-32.txt
U test/MC/Disassembler/X86/simple-tests.txt
D test/CodeGen/X86/bmi.ll
U lib/Target/X86/X86InstrInfo.td
U lib/Target/X86/X86ISelLowering.cpp
U lib/Target/X86/X86.td
U lib/Target/X86/X86Subtarget.h
llvm-svn: 141857
2011-10-13 07:48:07 +00:00
Craig Topper
eb29e18c9b
Add X86 TZCNT instruction and patterns to select it. Also added core-avx2 processor which is gcc's name for Haswell.
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llvm-svn: 141854
2011-10-13 07:09:14 +00:00
Craig Topper
c498c5c0e6
Add X86 LZCNT instruction. Including instruction selection support.
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llvm-svn: 141651
2011-10-11 06:44:02 +00:00
Craig Topper
7ae42fbd7e
Fix disassembling of popcntw. Also remove some code that says it accounts for 64BIT_REXW_XD not existing, but it does exist.
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llvm-svn: 141642
2011-10-11 04:34:23 +00:00
Craig Topper
9b7ab95570
Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler.
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llvm-svn: 141505
2011-10-09 07:31:39 +00:00
Craig Topper
761bf0e7d3
Add X86 disassembler support for RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE.
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llvm-svn: 141358
2011-10-07 07:02:24 +00:00
Craig Topper
71e09ffe7b
Add X86 disassembler support for XSAVE, XRSTOR, and XSAVEOPT.
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llvm-svn: 141354
2011-10-07 05:53:50 +00:00
Craig Topper
9d32602cfd
Add support in the disassembler for ignoring the L-bit on certain VEX instructions. Mark instructions that have this behavior. Fixes PR10676.
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llvm-svn: 141065
2011-10-04 06:30:42 +00:00
Craig Topper
df04bee9b2
Add support for MOVBE and RDRAND instructions for the assembler and disassembler. Includes feature flag checking, but no instrinsic support. Fixes PR10832, PR11026 and PR11027.
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llvm-svn: 141007
2011-10-03 17:28:23 +00:00
Craig Topper
4456c94f70
Treat VEX.vvvv as a 3-bit field outside of 64-bit mode. Prevents access to registers xmm8-xmm15 outside 64-bit mode.
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llvm-svn: 140997
2011-10-03 08:14:29 +00:00
Craig Topper
f776e3b410
Fix some Intel syntax disassembly issues with instructions that implicitly use AL/AX/EAX/RAX such as ADD/SUB/ADC/SUBB/XOR/OR/AND/CMP/MOV/TEST.
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llvm-svn: 140974
2011-10-02 21:08:12 +00:00
Craig Topper
5c8feca34f
Special case disassembler handling of REX.B prefix on NOP instruction to decode as XCHG R8D, EAX instead. Fixes PR10344.
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llvm-svn: 140971
2011-10-02 16:56:09 +00:00
Craig Topper
43fd621df8
Fix disassembling of INVEPT and INVVPID to take operands
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llvm-svn: 140955
2011-10-01 21:20:14 +00:00
Craig Topper
99ad3cc23e
Fix disassembler handling of CRC32 which is an odd instruction that uses 0xf2 as an opcode extension and allows the opsize prefix. This necessitated adding IC_XD_OPSIZE and IC_64BIT_XD_OPSIZE contexts. Unfortunately, this increases the size of the disassembler tables. Fixes PR10702.
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llvm-svn: 140954
2011-10-01 19:54:56 +00:00
Craig Topper
60719c7bfb
Fix mem type for VEX.128 form of VROUNDP*. Remove filter preventing VROUND from being recognized by disassembler.
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llvm-svn: 139691
2011-09-14 06:41:26 +00:00
Craig Topper
25e81ae604
Make disassembling of VBLEND* print immediate as a XMM/YMM register name. Fixes PR10917.
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llvm-svn: 139690
2011-09-14 05:55:28 +00:00
Craig Topper
03c833ff84
Remove filter that was preventing MOVDQU/MOVDQA and their VEX forms from being disassembled. Also added encodings for the other register/register form of these instructions. Fixes PR10848.
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llvm-svn: 139588
2011-09-13 06:54:58 +00:00
Craig Topper
5ffd0cb080
Fix disassembling of one of the register/register forms of MOVUPS/MOVUPD/MOVAPS/MOVAPD/MOVSS/MOVSD and their VEX equivalents. Fixes PR10877.
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llvm-svn: 139486
2011-09-11 23:19:54 +00:00
Craig Topper
a9b27eecc9
Fix disassembling of reverse register/register forms of ADD/SUB/XOR/OR/AND/SBB/ADC/CMP/MOV.
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llvm-svn: 139485
2011-09-11 21:41:45 +00:00