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72b1964108
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512 Commits

Author SHA1 Message Date
Chris Lattner
72b1964108 Fix a crash on 173.applu by asking for a constant bigger than 32-bits. 
llvm-svn: 21185
 2005-04-09 19:47:21 +00:00
Chris Lattner
c97f9f403f Switch this instruction selector over to using liveins and liveouts, eliminating 
implicit defs on entry to the function.  yaay :)

llvm-svn: 21184
 2005-04-09 16:32:30 +00:00
Nate Begeman
98bcb13bfa Optimize FSEL a bit for fneg arguments. This fixes the recently added test 
case so that we emit

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fsel f1, f1, f3, f2
        blr

instead of:

_test_fneg_sel:
.LBB_test_fneg_sel_0:   ;
        fneg f0, f1
        fneg f0, f0
        fsel f1, f0, f3, f2
        blr

llvm-svn: 21177
 2005-04-09 09:33:07 +00:00
Chris Lattner
c80baf5567 This target does not yet support ISD::BRCONDTWOWAY 
llvm-svn: 21163
 2005-04-09 03:22:30 +00:00
Nate Begeman
99fb6814bd 64b: Expand S/UREM 
32b: No longer pattern match fneg(fsub(fmul)) as fnmsub
     Pattern match fsub a, mul(b, c) as fnmsub
     Pattern match fadd a, mul(b, c) as fmadd
Those changes speed up hydro2d by 2.5%, distray by 6%, and scimark by 8%

llvm-svn: 21161
 2005-04-09 03:05:51 +00:00
Nate Begeman
95e1b860a1 Fix 64b shifts 
llvm-svn: 21159
 2005-04-08 23:45:01 +00:00
Nate Begeman
3fca499b8d Match Mac OS X 64 bit calling conventions 
llvm-svn: 21157
 2005-04-08 21:26:05 +00:00
Nate Begeman
6875356db1 Optimized code sequences for setcc reg, 0 
Optimized code sequence for (a < 0) ? b : 0

llvm-svn: 21150
 2005-04-07 20:30:01 +00:00
Chris Lattner
352dd3e579 PowerPC zero extends setcc results 
llvm-svn: 21147
 2005-04-07 19:41:49 +00:00
Nate Begeman
b890f32ac9 Pattern match bitfield insert, which helps shift long by immediate, among 
other things.

llvm-svn: 21127
 2005-04-06 23:51:40 +00:00
Nate Begeman
6c5e4c3bb1 Fix some shift bugs 
llvm-svn: 21126
 2005-04-06 22:42:08 +00:00
Nate Begeman
98251d6a1c Fixed version of optimized integer divide is now fixed. Calculate the 
quotient, not the remainder.  Also, make sure to remove the old div operand
from the ExprMap and let SelectExpr insert the new one.

llvm-svn: 21111
 2005-04-06 06:44:57 +00:00
Nate Begeman
aee0f81849 Turn off the div -> mul optimization until it works correctly 100% of the 
time.

llvm-svn: 21105
 2005-04-06 03:36:33 +00:00
Nate Begeman
b44597771c Add support for MULHS and MULHU nodes 
Have LegalizeDAG handle SREM and UREM for us
Codegen SDIV and UDIV by constant as a multiply by magic constant instead
of integer divide, which is very slow.

llvm-svn: 21104
 2005-04-06 00:25:27 +00:00
Nate Begeman
82ff41c342 Behold, rlwinm with certain immediate arguments is printed as the much more 
readable slwi or srwi (shift left/right word immediate).

llvm-svn: 21099
 2005-04-05 18:19:50 +00:00
Nate Begeman
581553fd21 Fix cut & paste errors (32->64), and codegen float->int more optimally. 
llvm-svn: 21098
 2005-04-05 17:32:30 +00:00
Nate Begeman
152dbbe856 Remove 64 bit simple ISel, it never worked correctly 
Add initial (buggy) implementation of 64 bit pattern ISel

llvm-svn: 21096
 2005-04-05 08:51:15 +00:00
Nate Begeman
a18a26f47c Back out the previous change to SelectBranchCC, since there are cases it 
could miscompile.  A correct solution will be found in the near future.

llvm-svn: 21095
 2005-04-05 04:32:16 +00:00
Nate Begeman
358dee806e Rename canUseAsImmediateForOpcode to getImmediateForOpcode to better 
indicate that it is not a boolean function.
Properly emit the pseudo instruction for conditional branch, so that we
  can fix up conditional branches whose displacements are too large.
Reserve the right amount of opcode space for said pseudo instructions.

llvm-svn: 21094
 2005-04-05 04:22:58 +00:00
Nate Begeman
ede4abc899 Implement SDIV by power of 2 as srawi/addze rather than load imm, divw 
llvm-svn: 21091
 2005-04-05 00:15:08 +00:00
Nate Begeman
00002553ba Pattern match fp mul-add, mul-sub, neg-mul-add, and neg-mul-sub 
llvm-svn: 21090
 2005-04-04 23:40:36 +00:00
Nate Begeman
682fd51f9c Add support for multiply-add, multiply-sub, and their negated versions 
llvm-svn: 21089
 2005-04-04 23:01:51 +00:00
Nate Begeman
d9af5c4fc5 Make sure that arg regs used by the call instruction are marked as such, so 
that regalloc doesn't cleverly reuse early arg regs loading later arg regs.
This fixes almost all outstanding failures in the pattern isel.

llvm-svn: 21086
 2005-04-04 22:17:48 +00:00
Nate Begeman
ce13bceb2a Remove unnecessary register copy now that regalloc is fixed 
llvm-svn: 21085
 2005-04-04 21:48:13 +00:00
Nate Begeman
bde3612ce3 i1 loads should also be from the low byte of the argument word. 
llvm-svn: 21077
 2005-04-04 09:09:00 +00:00
Nate Begeman
77427b1e77 Fix i64 return, fix CopyFromReg 
llvm-svn: 21076
 2005-04-04 06:52:38 +00:00
Nate Begeman
b2e5a962ff Full varargs support. All of UnitTests now passes 
llvm-svn: 21070
 2005-04-03 23:11:17 +00:00
Nate Begeman
1a5aaf6009 Pass the correct value for the chain to the store 
llvm-svn: 21066
 2005-04-03 22:22:56 +00:00
Nate Begeman
82d17d0e70 Fix SHL_PARTS 
Start implementation of integer varargs

llvm-svn: 21065
 2005-04-03 22:13:27 +00:00
Nate Begeman
127bd62534 Keeping up with the Joneses. 
Implement not, nor, nand, and eqv

llvm-svn: 21060
 2005-04-03 11:20:20 +00:00
Nate Begeman
402c04ff16 Set shift amount to Extend 
Implement ISD::FABS and ISD::FNEG nodes
Implement SHL_PARTS, SRL_PARTS, and SRA_PARTS
Generate PowerPC 'fneg', 'fabs', and 'fnabs' instructions

llvm-svn: 21018
 2005-04-02 05:59:34 +00:00
Chris Lattner
a5d4718875 This target doesn't support fabs/fneg yet. 
llvm-svn: 21010
 2005-04-02 05:03:24 +00:00
Nate Begeman
8d60ca616f Fix i64 returns 
Generate PowerPC 'subfic' instruction when appropriate

llvm-svn: 20995
 2005-04-02 00:42:16 +00:00
Nate Begeman
4034852ba9 Add ISD::UNDEF node 
Teach the SelectionDAG code how to expand and promote it
Have PPC32 LowerCallTo generate ISD::UNDEF for int arg regs used up by fp
  arguments, but not shadowing their value.  This allows us to do the right
  thing with both fixed and vararg floating point arguments.

llvm-svn: 20988
 2005-04-01 22:34:39 +00:00
Nate Begeman
244b36582a Fix Olden/bh, CR0 was being set in the wrong order 
LowerCallTo and ISD::CALL are going to need to be modified, regs are being
set in the wrong order.

llvm-svn: 20981
 2005-04-01 08:57:43 +00:00
Nate Begeman
f3ead25b68 Also apply Chris's fix to FP select and SETCC 
llvm-svn: 20979
 2005-04-01 07:21:30 +00:00
Chris Lattner
0cd0036523 Move the selection of the arms of the select operation up to the conditional 
part to make sure we get the side effects and to avoid confusing the CFG.

llvm-svn: 20977
 2005-04-01 07:10:02 +00:00
Nate Begeman
e82a2d7373 Fix stores to global addresses 
Fix calls with no arguments

llvm-svn: 20975
 2005-04-01 05:57:17 +00:00
Nate Begeman
9d224ae29b Support indexed loads and stores. This drops Shootout/matrix time from 
18.8 to 14.8 seconds.  The Pattern ISel is now often faster than the
Simple ISel, esp. on memory intensive code.

llvm-svn: 20973
 2005-04-01 04:45:11 +00:00
Nate Begeman
af7c6366d7 Implement FP_TO_SINT and FP_TO_UINT 
llvm-svn: 20972
 2005-04-01 02:59:27 +00:00
Nate Begeman
552f6f5f4e Add support for adding 0.0 and -0.0 to the constant pool, since we lie and 
say that we support them, for the purposes of generating fsel instructions.

llvm-svn: 20970
 2005-04-01 01:08:07 +00:00
Nate Begeman
18b3394f4d Factor out common code, support FP comparison in folded SetCC 
llvm-svn: 20969
 2005-04-01 00:32:34 +00:00
Nate Begeman
fc89059914 fsel generation for f32 and f64 select 
generate compare immediate for integer compare with constant
fold setcc into branch
fold setcc into select

Code generation quality for Shootout is now on par with the Simple ISel

llvm-svn: 20968
 2005-03-31 23:55:40 +00:00
Nate Begeman
17ff2b3a87 Pass the correct values to the chain argument for node construction during 
LowerCallTo.
Handle ISD::ADD in SelectAddr, allowing us to have nonzero immediates for
loads and stores, amazing!

llvm-svn: 20946
 2005-03-31 02:05:53 +00:00
Nate Begeman
de4aac1374 Rewrite LowerCallTo and Select(ISD::CALL) to properly handle float varargs 
Tell the SelectionDAG ISel to expand SEXTLOAD of i1 and i8, rather than
  complicate the code in ISD::SEXTLOAD to do it by hand
Combine the FP and Int ISD::LOAD codegen
Generate better code for constant pool loads

As a result, all of Shootout, and likely many other programs are now
working.

llvm-svn: 20945
 2005-03-31 00:15:26 +00:00
Nate Begeman
9c5480beeb Fix calls whose arguments fit entirely in registers to not break the Chain. 
Implement SINT_TO_FP and UINT_TO_FP
Remove some dead code from the simple ISel

llvm-svn: 20944
 2005-03-30 19:38:35 +00:00
Nate Begeman
c877844625 Fix frame index code to generate legal PowerPC instructions. About half of 
Shootout now works.

llvm-svn: 20940
 2005-03-30 02:23:08 +00:00
Nate Begeman
ec87399dac Fix external symbol printing in the AsmPrinter. Tell the ISel that we 
don't support things like memcpy directly.  This allows a handful of the
Shootout programs to work, yay!

llvm-svn: 20939
 2005-03-30 01:45:43 +00:00
Nate Begeman
8eddad3985 Fix BranchCC (it's still dumb), and implement FP select (also dumb) 
llvm-svn: 20935
 2005-03-29 22:48:55 +00:00
Nate Begeman
43b127ca0a Implement integer select and i1 sign extend 
llvm-svn: 20934
 2005-03-29 22:24:51 +00:00