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Author SHA1 Message Date
Jim Grosbach
ab5dbe090b Simplify operand Kind checks a bit. 
llvm-svn: 141592
 2011-10-10 23:06:42 +00:00
Bill Wendling
7121342ad5 Reapply r141365 now that PR11107 is fixed. 
llvm-svn: 141591
 2011-10-10 22:59:55 +00:00
Jim Grosbach
21a08a2b41 Add a name to sub-operand for clarity. 
llvm-svn: 141590
 2011-10-10 22:55:05 +00:00
Bill Wendling
9cf46b3bd5 If the CPSR is defined by a copy, then we don't want to merge it into an IT 
block. E.g., if we have:

  movs  r1, r1
  rsb   r1, 0
  movs  r2, r2
  rsb   r2, 0

we don't want this to be converted to:

  movs  r1, r1
  movs  r2, r2
  itt   mi
  rsb   r1, 0
  rsb   r2, 0

PR11107 & <rdar://problem/10259534>

llvm-svn: 141589
 2011-10-10 22:52:53 +00:00
Eli Friedman
7188ba35cb Make sure the X86 backend doesn't explode on 128-bit shuffles in AVX mode. Fixes PR11102. 
llvm-svn: 141585
 2011-10-10 22:28:47 +00:00
Michael J. Spencer
ebd507f958 Object: add getSectionAlignment. 
llvm-svn: 141581
 2011-10-10 21:55:43 +00:00
Nick Lewycky
73e4d372d0 Add support for dumping section headers to llvm-objdump. This uses the same 
flags as binutils objdump but the output is different, not just in format but
also showing different sections. Compare its results against readelf, not
objdump.

llvm-svn: 141579
 2011-10-10 21:21:34 +00:00
Jakob Stoklund Olesen
0d908f3a85 Give targets a chance to expand even standard pseudos. 
Allow targets to expand COPY and other standard pseudo-instructions
before they are expanded with copyPhysReg().

This allows the target to examine the COPY instruction for extra
operands indicating it can be widened to a preferable super-register
copy.  See the ARM -widen-vmovs option.

llvm-svn: 141578
 2011-10-10 20:34:28 +00:00
Devang Patel
d6f05a47c1 If loop header is also loop exiting block then it may not be safe to hoist instructions. 
llvm-svn: 141576
 2011-10-10 20:32:03 +00:00
Jakob Stoklund Olesen
ad7ffa5235 Emit full ED initializers even for pseudo-instructions. 
This should unbreak the picky buildbots.

llvm-svn: 141575
 2011-10-10 20:15:49 +00:00
Andrew Trick
4c8a7dc833 Allow stat += 0 without activating the stat. 
For me, this is a nice convenience. We generally want grep to match
stats output only when the event has occurred.

llvm-svn: 141574
 2011-10-10 19:48:56 +00:00
Andrew Trick
fe8c38a61e whitespace 
llvm-svn: 141572
 2011-10-10 19:35:46 +00:00
Benjamin Kramer
60387b6640 X86: Add a subtarget definition for core-avx-i, which is GCC's name for ivy bridge. 
llvm-svn: 141571
 2011-10-10 19:35:07 +00:00
Nadav Rotem
38187aec17 Fix 10892 - When lowering SIGN_EXTEND_INREG do not lower v2i64 because the 
instruction set has no 64-bit SRA support.

llvm-svn: 141570
 2011-10-10 19:31:45 +00:00
Devang Patel
c149f390c6 Add dominance check for the instruction being hoisted. 
For example, MachineLICM should not hoist a load that is not guaranteed to be executed.
Radar 10254254.

llvm-svn: 141569
 2011-10-10 19:09:20 +00:00
Jakob Stoklund Olesen
bfbf896107 Mark the standard pseudos as isPseudo = 1. 
The difference between isPseudo and isCodeGenOnly is a bit murky, but
isCodeGenOnly should eventually go away.  It is used for instructions
that are clones of real instructions with slightly different properties.

The standard pseudo-instructions never mirror real instructions, so they
are definitely in the isPseudo category.

llvm-svn: 141567
 2011-10-10 18:51:33 +00:00
Bruno Cardoso Lopes
fa8f5fb2cf The Mips specific function for instruction cache invalidation cannot be 
compiled on mips32r1 processors because it uses synci and rdhwr instructions
which are supported only on mips32r2, so I replaced this function with the
call to function cacheflush which works for both mips32r1 and mips32r2.
Patch by Sasa Stankovic

llvm-svn: 141564
 2011-10-10 18:41:02 +00:00
Benjamin Kramer
c498279bec X86: Add patterns for the movbe instruction (mov + bswap, only available on atom) 
llvm-svn: 141563
 2011-10-10 18:34:56 +00:00
Jakob Stoklund Olesen
f46c756068 Insert dummy ED table entries for pseudo-instructions. 
The table is indexed by opcode, so simply removing pseudo-instructions
creates a wrong mapping from opcode to table entry.

Add a test case for xorps which has a very high opcode that exposes this
problem.

llvm-svn: 141562
 2011-10-10 18:30:16 +00:00
Bill Wendling
7cba44defc Revert r141365. It was causing MultiSource/Benchmarks/MiBench/consumer-lame to 
hang, and possibly SPEC/CINT2006/464_h264ref.

llvm-svn: 141560
 2011-10-10 18:27:30 +00:00
Owen Anderson
40a0b83c92 MCAtom extending methods need to extend the range of the atom as well. 
llvm-svn: 141557
 2011-10-10 18:09:38 +00:00
Bill Wendling
d7cb53193a Mark the llvm.eh.sjlj.functioncontext intrinsic as reading memory so that fast 
isel doesn't ignore it.

llvm-svn: 141548
 2011-10-10 17:08:47 +00:00
Benjamin Kramer
05836b12fd llvm-objdump: Take ownership of MCInstrInfos. 
llvm-svn: 141535
 2011-10-10 13:10:09 +00:00
Benjamin Kramer
357893ba6f llvm-nm: Don't leak bitcode buffers. 
llvm-svn: 141534
 2011-10-10 13:10:04 +00:00
Benjamin Kramer
abcce0b8be XFAIL tblgen tests on leak checkers. 
llvm-svn: 141533
 2011-10-10 13:09:59 +00:00
Bill Wendling
94258753c7 When getting the number of bits necessary for addressing mode 
ARMII::AddrModeT1_s, we need to take into account that if the frame register is
ARM::SP, then the number of bits is 8. If it's not ARM::SP, then the number of
bits is 5.

llvm-svn: 141529
 2011-10-10 07:24:23 +00:00
Craig Topper
251bbfb1f7 Put a bunch of calls to ToggleFeature behind proper if statements. 
llvm-svn: 141527
 2011-10-10 05:34:02 +00:00
Chad Rosier
2fc181986a Fix a regression from r138445. If we're loading from the frame/base pointer 
the tADDrSPi instruction can't be used.  Make sure we're updating the opcode
to tADDi3 in all cases.
rdar://10254707

llvm-svn: 141523
 2011-10-10 01:03:35 +00:00
Justin Holewinski
ce14c646cd PTX: Print .ptr kernel attributes if PTX version >= 2.2 
llvm-svn: 141508
 2011-10-09 15:42:02 +00:00
Craig Topper
9b7ab95570 Add Ivy Bridge 16-bit floating point conversion instructions for the X86 disassembler. 
llvm-svn: 141505
 2011-10-09 07:31:39 +00:00
Jakob Stoklund Olesen
d94788edb9 Prevent potential NOREX bug. 
A GR8_NOREX virtual register is created when extrating a sub_8bit_hi
sub-register:

  %vreg2<def> = COPY %vreg1:sub_8bit_hi; GR8_NOREX:%vreg2 %GR64_ABCD:%vreg1
  TEST8ri_NOREX %vreg2, 1, %EFLAGS<imp-def>; GR8_NOREX:%vreg2

If such a live range is ever split, its register class must not be
inflated to GR8.  The sub-register copy can only target GR8_NOREX.

I dont have a test case for this theoretical bug.

llvm-svn: 141500
 2011-10-08 20:20:03 +00:00
Jakob Stoklund Olesen
b49557d06d Add TEST8ri_NOREX pseudo to constrain sub_8bit_hi copies. 
In 64-bit mode, sub_8bit_hi sub-registers can only be used by NOREX
instructions. The COPY created from the EXTRACT_SUBREG DAG node cannot
target all GR8 registers, only those in GR8_NOREX.

TO enforce this, we ensure that all instructions using the
EXTRACT_SUBREG are GR8_NOREX constrained.

This fixes PR11088.

llvm-svn: 141499
 2011-10-08 18:28:28 +00:00
Jakob Stoklund Olesen
2817bbdeaf Add missing test case for r141410. 
llvm-svn: 141498
 2011-10-08 18:06:54 +00:00
Benjamin Kramer
22607ddb94 Include direct.h for _mkdir on mingw32 too. 
llvm-svn: 141495
 2011-10-08 15:49:19 +00:00
Che-Liang Chiou
c1ba72e15c Revert r141079: tblgen: add preprocessor as a separate mode 
llvm-svn: 141492
 2011-10-08 12:39:26 +00:00
Nicolas Geoffray
8c7ad22407 Always check if a method or a type exist before trying to create it. 
llvm-svn: 141490
 2011-10-08 11:56:36 +00:00
NAKAMURA Takumi
2a3eab692a lib/Object: Suppress warnings on gcc-4.3.4 cygwin 
llvm-svn: 141485
 2011-10-08 11:22:53 +00:00
NAKAMURA Takumi
cc0706b36c lib/DebugInfo/DWARFDebugLine.cpp: De-Unicode-ify. 
llvm-svn: 141484
 2011-10-08 11:22:47 +00:00
NAKAMURA Takumi
fe47764929 Whitespace 
llvm-svn: 141483
 2011-10-08 11:22:41 +00:00
Anton Korobeynikov
b0534f0113 Disable ABS optimization for Thumb1 target, we don't have necessary instructions there. 
llvm-svn: 141481
 2011-10-08 08:38:45 +00:00
Akira Hatanaka
4a78bb776f Simplify definition of FP move instructions. 
llvm-svn: 141476
 2011-10-08 03:50:18 +00:00
Akira Hatanaka
7780dcc74e Define classes and multiclasses for FP binary instructions. 
llvm-svn: 141475
 2011-10-08 03:38:41 +00:00
Akira Hatanaka
9595e84a11 Define multiclasses for FP-to-FP instructions. 
llvm-svn: 141474
 2011-10-08 03:29:22 +00:00
Akira Hatanaka
e39c39db4a Define classes for FP unary instructions and multiclasses for FP-to-fixed point 
conversion instructions. 

llvm-svn: 141473
 2011-10-08 03:19:38 +00:00
Andrew Trick
9d4d1281ad Unit test for LSR phi reuse in r141442. 
llvm-svn: 141472
 2011-10-08 02:34:51 +00:00
Akira Hatanaka
38d2ddcfac Add patterns for unaligned load and store instructions and enable the 
instruction selector to generate them.

llvm-svn: 141471
 2011-10-08 02:24:10 +00:00
Andrew Trick
430029d79a Add an extra safety check in front of the optimization in r141442. 
llvm-svn: 141470
 2011-10-08 02:16:39 +00:00
Bill Wendling
a2a555b0fc Use the code that lowers the arguments and spills any values which are alive 
across unwind edges. This is for the back-end which expects such things.

The code is from the original SjLj EH pass.

llvm-svn: 141463
 2011-10-08 00:56:47 +00:00
Peter Collingbourne
da02db0a55 Add clang-tblgen to OPTIONAL_DIRS when building native tools for the 
cross build, so that a native version of clang-tblgen is available.
Should unbreak Clang cross build.

Also disable Polly for the native tool build, since it depends on
external libraries which may not be available, and it isn't required
anyway.

llvm-svn: 141454
 2011-10-08 00:27:38 +00:00
Michael J. Spencer
e497728e76 llvm-objdump: Add relocation and archive support. 
llvm-svn: 141451
 2011-10-08 00:18:30 +00:00