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12 Commits

Author SHA1 Message Date
Hal Finkel
0673920af6 Add PPC Freescale e500mc and e5500 subtargets. 
Add subtargets for Freescale e500mc (32-bit) and e5500 (64-bit) to
the PowerPC backend.

Patch by Tobias von Koch.

llvm-svn: 162764
 2012-08-28 16:12:39 +00:00
Hal Finkel
a65f8ac557 Split several PPC instruction classes. 
Slight reorganisation of PPC instruction classes for scheduling. No
functionality change for existing subtargets.
 - Clearly separate load/store-with-update instructions from regular loads and stores.
 - Split IntRotateD -> IntRotateD and IntRotateDI
 - Split out fsub and fadd from FPGeneral -> FPAddSub
 - Update existing itineraries

Patch by Tobias von Koch.

llvm-svn: 162729
 2012-08-28 02:49:14 +00:00
Hal Finkel
a005be7ae7 Split out the PPC instruction class IntSimple from IntGeneral. 
On the POWER7, adds and logical operations can also be handled
in the load/store pipelines. We'll call these IntSimple.

llvm-svn: 158366
 2012-06-12 19:01:24 +00:00
Hal Finkel
fd26145bc6 Add instruction itinerary for the PPC64 A2 core. 
This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

llvm-svn: 153842
 2012-04-01 19:22:40 +00:00
Hal Finkel
42a487282a Split the LdStGeneral PPC itin. class into LdStLoad and LdStStore. 
Loads and stores can have different pipeline behavior, especially on
embedded chips. This change allows those differences to be expressed.
Except for the 440 scheduler, there are no functionality changes.
On the 440, the latency adjustment is only by one cycle, and so this
probably does not affect much. Nevertheless, it will make a larger
difference in the future and this removes a FIXME from the 440 itin.

llvm-svn: 153821
 2012-04-01 04:44:16 +00:00
Jia Liu
b077b6085d Emacs-tag and some comment fix for all ARM, CellSPU, Hexagon, MBlaze, MSP430, PPC, PTX, Sparc, X86, XCore. 
llvm-svn: 150878
 2012-02-18 12:03:15 +00:00
Hal Finkel
74543873a4 Add PPC 440 scheduler and some associated tests 
llvm-svn: 142170
 2011-10-17 04:03:49 +00:00
Anton Korobeynikov
e325c693a5 Make processor FUs unique for given itinerary. This extends the limit of 32 
FU per CPU arch to 32 per intinerary allowing precise modelling of quite
complex pipelines in the future.

llvm-svn: 101754
 2010-04-18 20:31:01 +00:00
Chris Lattner
ad9a6ccb83 Remove attribution from file headers, per discussion on llvmdev. 
llvm-svn: 45418
 2007-12-29 20:36:04 +00:00
Jim Laskey
514a74d946 Added InstrSchedClass to each of the PowerPC Instructions. 
Note that when adding new instructions that you should refer to the table at the
bottom of PPCSchedule.td.

llvm-svn: 23830
 2005-10-19 19:51:16 +00:00
Jim Laskey
0918760dec Push processor descriptions to the top of target and add command line info. 
llvm-svn: 23820
 2005-10-19 13:34:52 +00:00
Jim Laskey
610af28ca0 Checking in first round of scheduling tablegen files. Not tied in as yet. 
llvm-svn: 23786
 2005-10-18 16:23:40 +00:00