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Author SHA1 Message Date
Evan Cheng
19550821d1 Added some isel ideas. 
llvm-svn: 24757
 2005-12-17 01:25:19 +00:00
Evan Cheng
5d90b26707 Added support for cmp, test, and conditional move instructions. 
llvm-svn: 24756
 2005-12-17 01:24:02 +00:00
Evan Cheng
566600c17d Only lower SELECT when using DAG based isel. 
llvm-svn: 24755
 2005-12-17 01:22:13 +00:00
Evan Cheng
d51da93a03 X86 lowers SELECT to a cmp / test followed by a conditional move. 
llvm-svn: 24754
 2005-12-17 01:21:05 +00:00
Evan Cheng
54695fd38d Support for read / write from explicit registers with FlagVT type. 
llvm-svn: 24753
 2005-12-17 01:19:28 +00:00
Jeff Cohen
19d804b6d6 Fix VC++ level 4 warnings. Because a base class has declared these private, VC++ complains it cannot automatically generate this methods. 
llvm-svn: 24751
 2005-12-17 00:19:22 +00:00
Jeff Cohen
0998a3e70e Fix VC++ level 4 warnings. 
llvm-svn: 24750
 2005-12-17 00:18:06 +00:00
Jeff Cohen
f9fecfca82 Turn on string pooling for smaller binaries. 
llvm-svn: 24749
 2005-12-17 00:14:47 +00:00
Jim Laskey
37957b1ad3 Added source file/line correspondence for dwarf (PowerPC only at this point.) 
llvm-svn: 24748
 2005-12-16 22:45:29 +00:00
Chris Lattner
ba98d302be Weak and linkonce global vars should still have a .globl emitted for them 
llvm-svn: 24747
 2005-12-16 21:46:14 +00:00
Nate Begeman
69da94a1b9 Add a second vector type to the VRRC register class, and fix some patterns 
so that tablegen can infer all types.

llvm-svn: 24746
 2005-12-16 09:19:13 +00:00
Chris Lattner
2c9fd95c73 add some notes 
llvm-svn: 24745
 2005-12-16 07:20:53 +00:00
Chris Lattner
86914b7f4e Add a couple more instrs 
llvm-svn: 24744
 2005-12-16 07:18:48 +00:00
Chris Lattner
29c644f929 remove some dead code 
llvm-svn: 24743
 2005-12-16 07:16:02 +00:00
Chris Lattner
a7ead87ba4 asmprint pseudo instrs 
llvm-svn: 24742
 2005-12-16 07:13:26 +00:00
Chris Lattner
16896ce1ed Autogenerate asmprinter for F3_2 instructions 
llvm-svn: 24741
 2005-12-16 07:10:02 +00:00
Chris Lattner
b9b7b057d6 Switch F3_1 instructions over to use AsmStrings 
llvm-svn: 24740
 2005-12-16 06:52:00 +00:00
Chris Lattner
8fd4bf0ac7 Plug in basic hooks for an autogenerated asm printer to fill in. 
llvm-svn: 24739
 2005-12-16 06:34:17 +00:00
Chris Lattner
60e5e47904 Add operand info for F3_[12] instructions, getting V8 back to basic functionality. 
With this, Regression/CodeGen/SparcV8/basictest.ll now passes.  Lets hear it
for regression tests :)

llvm-svn: 24738
 2005-12-16 06:25:42 +00:00
Chris Lattner
bf9467792f A truly trivial testcase to ensure sparcv8 doesn't get completely broken 
again.

llvm-svn: 24737
 2005-12-16 06:24:55 +00:00
Chris Lattner
44de5f7807 Remove JIT support, which doesn't work. 
llvm-svn: 24736
 2005-12-16 06:06:07 +00:00
Chris Lattner
a795cdbfcd add some simple operand info 
llvm-svn: 24735
 2005-12-16 06:02:58 +00:00
Chris Lattner
9823998a84 rename option for consistency with -mcpu -mattr etc 
llvm-svn: 24734
 2005-12-16 05:19:55 +00:00
Chris Lattner
33270e3183 rename options 
llvm-svn: 24733
 2005-12-16 05:19:35 +00:00
Chris Lattner
06de420b3c rename option 
llvm-svn: 24732
 2005-12-16 05:19:18 +00:00
Chris Lattner
d378f50187 Document -mcpu -mattr -triple 
llvm-svn: 24731
 2005-12-16 05:18:53 +00:00
Chris Lattner
ad407557f7 provide an option to override the target triple in a module from the commandline. 
llvm-svn: 24730
 2005-12-16 05:00:21 +00:00
Chris Lattner
073c670431 provide an option to override the target triple in a module from the command 
line.

llvm-svn: 24729
 2005-12-16 04:59:57 +00:00
Chris Lattner
890fd4e66c Update the darwin handling of linkonce & weak functions and GV stubs. This 
should work in all permutations.

llvm-svn: 24728
 2005-12-16 00:22:14 +00:00
Chris Lattner
71443a0e36 Don't globalize internal functions 
llvm-svn: 24727
 2005-12-16 00:07:30 +00:00
Evan Cheng
43152cb8b6 * Promote all 1 bit entities to 8 bit. 
* Handling extload (1 bit -> 8 bit) and remove C++ code that handle 1 bit
zextload.

llvm-svn: 24726
 2005-12-15 19:49:23 +00:00
Chris Lattner
d4a3cb4d86 Don't create SEXTLOAD/ZEXTLOAD instructions that the target doesn't support 
if after legalize.  This fixes IA64 failures.

llvm-svn: 24725
 2005-12-15 19:02:38 +00:00
Evan Cheng
f72e7055c0 Added frameindex, constpool, globaladdr, and externalsym as root nodes of 
leaaddr.

llvm-svn: 24724
 2005-12-15 08:31:04 +00:00
Evan Cheng
9c0d7cacf7 Added constpool, frameindex, and externalsym nodes. 
llvm-svn: 24723
 2005-12-15 08:29:48 +00:00
Evan Cheng
cc6efa8b6f Handling zero extension of 1 bit value. 
llvm-svn: 24722
 2005-12-15 01:02:48 +00:00
Evan Cheng
576b826f71 Use MOV8rm to load 1 bit value. 
llvm-svn: 24721
 2005-12-15 00:59:17 +00:00
Nate Begeman
f5ac708070 Remove a now unused statistic. 
llvm-svn: 24720
 2005-12-14 22:56:16 +00:00
Nate Begeman
fe7a3f28e3 Use the new predicate support that Evan Cheng added to remove some code 
from the DAGToDAG cpp file.  This adds pattern support for vector and
scalar fma, which passes test/Regression/CodeGen/PowerPC/fma.ll, and
does the right thing in the presence of -disable-excess-fp-precision.

Allows us to match:
void %foo(<4 x float> * %a) {
entry:
  %tmp1 = load <4 x float> * %a;
  %tmp2 = mul <4 x float> %tmp1, %tmp1
  %tmp3 = add <4 x float> %tmp2, %tmp1
  store <4 x float> %tmp3, <4 x float> *%a
  ret void
}

As:

_foo:
        li r2, 0
        lvx v0, r2, r3
        vmaddfp v0, v0, v0, v0
        stvx v0, r2, r3
        blr

Or, with llc -disable-excess-fp-precision,

_foo:
        li r2, 0
        lvx v0, r2, r3
        vxor v1, v1, v1
        vmaddfp v1, v0, v0, v1
        vaddfp v0, v1, v0
        stvx v0, r2, r3
        blr

llvm-svn: 24719
 2005-12-14 22:54:33 +00:00
Nate Begeman
ff176f341e Add a case for float just to make sure the patterns for both precisions 
are matching

llvm-svn: 24718
 2005-12-14 22:51:13 +00:00
Evan Cheng
40e397521c Fixed a typo: line 2323: MOVSX16rm8 -> MOVZX16rm8. This was the cause fo 12/14/2005 hbd failure. 
llvm-svn: 24717
 2005-12-14 22:28:18 +00:00
Evan Cheng
fbc29bb3dd Added predicate !NoExcessFPPrecision to FMADD, FMADDS, FMSUB, and FMSUBS. 
llvm-svn: 24716
 2005-12-14 22:07:12 +00:00
Evan Cheng
297c23d2e7 Added support to specify predicates. 
llvm-svn: 24715
 2005-12-14 22:02:59 +00:00
Chris Lattner
2c346c9a4b Fix printing of the instructions. 
llvm-svn: 24714
 2005-12-14 22:01:07 +00:00
Evan Cheng
bcdd22c501 Fixed extload type profile. The 4th operand is a ValueType node with type 
OtherVT, it cannot be compare to type of 1st operand which is an integer type.

llvm-svn: 24713
 2005-12-14 19:40:54 +00:00
Chris Lattner
9bdaf3e826 When folding loads into ops, immediately replace uses of the op with the 
load.  This reduces number of worklist iterations and avoid missing optimizations
depending on folding of things into sext_inreg nodes (which aren't supported by
all targets).
Tested by Regression/CodeGen/X86/extend.ll:test2

llvm-svn: 24712
 2005-12-14 19:25:30 +00:00
Chris Lattner
696d16afce new testcase, each function should have one extension instr in it 
llvm-svn: 24711
 2005-12-14 19:24:08 +00:00
Reid Spencer
5b1da8f9d0 Remove -start-group and -end-group no-op options, accidentally committed 
in last patch.

llvm-svn: 24710
 2005-12-14 19:08:51 +00:00
Chris Lattner
790a35b33b Fix the (zext (zextload)) case to trigger, similarly for sign extends. 
Allow (zext (truncate)) to apply after legalize if the target supports
AND (which all do).

This compiles
short %foo() {
        %tmp.0 = load ubyte* %X         ; <ubyte> [#uses=1]
        %tmp.3 = cast ubyte %tmp.0 to short             ; <short> [#uses=1]
        ret short %tmp.3
}

to:
_foo:
        movzbl _X, %eax
        ret

instead of:

_foo:
        movzbl _X, %eax
        movzbl %al, %eax
        ret

thanks to Evan for pointing this out.

llvm-svn: 24709
 2005-12-14 19:05:06 +00:00
Chris Lattner
76b2303521 Fix Transforms/ScalarRepl/2005-12-14-UnionPromoteCrash.ll, a crash on undefined 
behavior in 126.gcc on big-endian systems.

llvm-svn: 24708
 2005-12-14 17:23:59 +00:00
Chris Lattner
d4d067561f new (undefined) testcase, distilled from 126.gcc that scalarrepl crashes on 
llvm-svn: 24707
 2005-12-14 17:23:20 +00:00