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Commit Graph

209861 Commits

Author SHA1 Message Date
Amara Emerson
8c25e6302a [AArch64][GlobalISel] Assign FPR banks to loads which are used by integer->float conversions.
G_[US]ITOFP users of loads on AArch64 can operate on both gpr and fpr banks for scalars.
Because of this, if their source is a load, then that load can be assigned to an fpr
bank and therefore avoid having to do a cross bank copy via a gpr->fpr conversion.

Differential Revision: https://reviews.llvm.org/D94701
2021-01-14 16:33:34 -08:00
Sanjay Patel
47b85ad366 [SLP] remove unnecessary state in matching reductions
This is NFC-intended. I'm still trying to figure out
how the loop where this is used works. It does not
seem like we require this data at all, but it's
hard to confirm given the complicated predicates.
2021-01-14 18:32:37 -05:00
Sam Elliott
bbb712770e [RISCV][NFC] Regenerate Calling Convention Tests
This regenerates these tests using utils/update_llc_test_checks.py so
that future changes in this area don't have the noise of lots of `@plt`
lines being added.

I also removed the `nounwind`s from the stack-realignment.ll test to
increase coverage on the generated call frame information.
2021-01-14 22:35:17 +00:00
Teresa Johnson
a9dfa4319c [LTO] Test format fix (NFC)
As requested in D91583, use ';;' instead of ';' to preceed comments in
lld test. I did this in the equivalent gold test as well.
2021-01-14 14:09:50 -08:00
Alexandre Ganea
11bbe8413e Re-land [Support] On Windows, take the affinity mask into account
The number of hardware threads available to a ThreadPool can be limited if setting an affinity mask.
For example:

    > start /B /AFFINITY 0xF lld-link.exe ...

Would let LLD only use 4 hyper-threads.

Previously, there was an outstanding issue on Windows Server 2019 on dual-CPU machines, which was preventing from using both CPU sockets. In normal conditions, when no affinity mask was set, ProcessorGroup::AllThreads was different from ProcessorGroup::UsableThreads. The previous code in llvm/lib/Support/Windows/Threading.inc L201 was improperly assuming those two values to be equal, and consequently was limiting the execution to only one CPU socket.

Differential Revision: https://reviews.llvm.org/D92419
2021-01-14 17:03:22 -05:00
Craig Topper
4b3a70fc30 [RISCV] Optimize select_cc after fp compare expansion
Some FP compares expand to a sequence ending with (xor X, 1) to invert the result. If
the consumer is a select_cc we can likely get rid of this xor by fixing
up the select_cc condition.

This patch combines (select_cc (xor X, 1), 0, setne, trueV, falseV) -
(select_cc X, 0, seteq, trueV, falseV) if we can prove X is 0/1.

Reviewed By: lenary

Differential Revision: https://reviews.llvm.org/D94546
2021-01-14 13:41:40 -08:00
Nico Weber
b1b4ed33f2 [gn build] (manually) port 387d3c24792f 2021-01-14 16:19:25 -05:00
Jinsong Ji
1232463119 [PowerPC] Only use some extend mne if assembler is modern enough
Legacy AIX assembly might not support all extended mnes,
add one feature bit to control the generation in MC,
and avoid generating them by default on AIX.

Reviewed By: sfertile

Differential Revision: https://reviews.llvm.org/D94458
2021-01-14 20:36:10 +00:00
Craig Topper
59b81ce9c2 [RISCV] Merge Utils library into MCTargetDesc
MCTargetDesc includes headers from Utils and Utils includes headers
from MCTargetDesc. So from a library layering perspective it makes sense
for them to be in the same library. I guess the other option might be to
move the tablegen includes from RISCVMCTargetDesc.h to RISCVBaseInfo.h
so that RISCVBaseInfo.h didn't need to include RISCVMCTargetDesc.h.
Everything else that depends on Utils also depends on MCTargetDesc so
having one library seemed simpler.

Differential Revision: https://reviews.llvm.org/D93168
2021-01-14 11:47:30 -08:00
Nikita Popov
d7b14864e8 [BasicAA] Handle recursive queries more efficiently
An alias query currently works out roughly like this:

 * Look up location pair in cache.
 * Perform BasicAA logic (including cache lookup and insertion...)
 * Perform a recursive query using BestAAResults.
   * Look up location pair in cache (and thus do not recurse into BasicAA)
   * Query all the other AA providers.
 * Query all the other AA providers.

This is a lot of unnecessary work, all ultimately caused by the
BestAAResults query at the end of aliasCheck(). The reason we perform
it, is that aliasCheck() is getting called recursively, and we of
course want those recursive queries to also make use of other AA
providers, not just BasicAA. We can solve this by making the recursive
queries directly use BestAAResults (which will check both BasicAA
and other providers), rather than recursing into aliasCheck().

There are some tradeoffs:

 * We can no longer pass through the precomputed underlying object
   to aliasCheck(). This is not a major concern, because nowadays
   getUnderlyingObject() is quite cheap.
 * Results from other AA providers are no longer cached inside
   BasicAA. The way this worked was already a bit iffy, in that a
   result could be cached, but if it was MayAlias, we'd still end
   up re-querying other providers anyway. If we want to cache
   non-BasicAA results, we should do that in a more principled manner.

In any case, despite those tradeoffs, this works out to be a decent
compile-time improvment. I think it also simplifies the mental model
of how BasicAA works. It took me quite a while to fully understand
how these things interact.

Differential Revision: https://reviews.llvm.org/D90094
2021-01-14 20:32:41 +01:00
Valentin Clement
53b440883c [openacc] Rename generated file from ACC.cpp.inc to ACC.inc to match D92955
This patch rename the tablegen generated file ACC.cpp.inc to ACC.inc in order
to match what was done in D92955. This file is included in header file as well as .cpp
file so it make more sense.

Reviewed By: sameeranjoshi

Differential Revision: https://reviews.llvm.org/D93485
2021-01-14 14:19:53 -05:00
Hiroshi Yamauchi
f8c8db7132 [X86] Add the FSRM feature (Fast Short Rep Mov) to Zen3.
Note -x86-use-fsrm-for-memcpy is still disabled by default and there's no
default behavior change.

Differential Revision: https://reviews.llvm.org/D94436
2021-01-14 10:47:33 -08:00
Jay Foad
af89a9efaf [SelectionDAG] Remove an early-out from computeKnownBits for smin/smax
Even if we know nothing about LHS, it can still be useful to know that
smax(LHS, RHS) >= RHS and smin(LHS, RHS) <= RHS.

Differential Revision: https://reviews.llvm.org/D87145
2021-01-14 18:15:17 +00:00
Simon Pilgrim
79bc4c8e7b [X86][AVX] Adjust unsigned saturation downconvert negative test
D87145 was showing that this test (added in D45315) could always be constant folded (with suitable value tracking).

What we actually needed was smax(smin()) negative test coverage, the invert of negative_test2_smax_usat_trunc_wb_256_mem, so I've tweaked the test to provide that instead.
2021-01-14 17:51:23 +00:00
Arthur Eubanks
3ceef7fba8 [NewPM] Fix placement of LoopFlatten
https://reviews.llvm.org/D90402 was inconsistent with where it put
LoopFlatten between the two pass managers. It also missed adding it to
the non-O1 function simplification pipeline.

PR48738

Reviewed By: SjoerdMeijer

Differential Revision: https://reviews.llvm.org/D94650
2021-01-14 09:49:31 -08:00
Mircea Trofin
53700188da [NFC] Disallow unused prefixes under MC/AArch64
Differential Revision: https://reviews.llvm.org/D94616
2021-01-14 09:46:13 -08:00
LLVM GN Syncbot
9ef2e47fbb [gn build] Port 2f395b7092bd 2021-01-14 17:39:58 +00:00
Mircea Trofin
a0cb30e00e [NFC] Disallow unused prefixes under MC/ARM
Differential Revision: https://reviews.llvm.org/D94620
2021-01-14 08:56:45 -08:00
Sam Elliott
ef0a591f9e Revert "[RISCV] Legalize select when Zbt extension available"
We found issues with this patch in additional testing. Backing out while
we work on a fix.

This reverts commit 71ed4b6ce57d8843ef705af8f98305976a8f107a.
2021-01-14 16:44:34 +00:00
Simon Pilgrim
9d1a22fca2 [SystemZ] misched-cutoff tests can only be tested on non-NDEBUG (assertion) builds
Fixes clang-with-thin-lto-ubuntu buildbot after D94383/rGddd03842c347
2021-01-14 15:46:27 +00:00
Simon Pilgrim
6c0e513e08 [Support] Remove redundant sign bit tests from KnownBits::getSignedMinValue/getSignedMaxValue
As noted by @foad on rG6895581fd2c1
2021-01-14 15:46:26 +00:00
Martin Storsjö
b30a8c6f0a Revert "[AArch64] Attempt to sink mul operands"
This reverts commit dda60035e9f0769c8907cdf6561489e0435c2275.

This commit caused failures to compile some sources, erroring out
with "error in backend: Cannot select: t85: v2i32 = AArch64ISD::DUP t15",
see https://reviews.llvm.org/D91271 for the full reproduction case.
2021-01-14 17:28:18 +02:00
Paul C. Anagnostopoulos
515dc94489 [TableGen] Enhance !cast<string> to handle bit and bits types.
Add a test for this.

Differential Revision: https://reviews.llvm.org/D94529
2021-01-14 10:20:35 -05:00
Simon Pilgrim
7e844422ba [Support] Simplify KnownBits::sextInReg implementation.
As noted by @foad in rG9cf4f493a72f all we need to do is sextInReg both KnownBits One and Zero.
2021-01-14 15:14:32 +00:00
Simon Pilgrim
0e743a4a45 [Support] Ensure KnownBits::sextInReg can handle the src == dst sext-in-reg case.
This was resulting in assertions inside APInt::zext that we were extending to the same bitwidth.
2021-01-14 14:50:21 +00:00
Stefan Gränitz
7d83b7c4c8 [docs] Update DebuggingJITedCode page after fix in LLDB
Generalize the documentation to include both, GDB and LLDB. Add a link to the interface
definition. Make a note on MCJIT's restriction to ELF. Mention the regression and bugfix
in LLDB as well as the jit-loader setting for macOS. Update the command line session to
use LLDB instead of GDB.

Reviewed By: lhames

Differential Revision: https://reviews.llvm.org/D90789
2021-01-14 15:43:11 +01:00
Simon Pilgrim
0e8dbbda98 [Support] Add KnownBits::sextInReg exhaustive tests
Requested by @foad in rG9cf4f493a72f
2021-01-14 14:27:45 +00:00
Jay Foad
817ed0fdbd [Support] Simplify KnownBits::icmp helpers. NFC.
Remove some special cases that aren't really any simpler than the
general case.

Differential Revision: https://reviews.llvm.org/D94595
2021-01-14 14:02:43 +00:00
Jay Foad
541d0407ff [Analysis,CodeGen] Make use of KnownBits::makeConstant. NFC.
Differential Revision: https://reviews.llvm.org/D94588
2021-01-14 14:02:43 +00:00
Jay Foad
3959fb7bf5 [SelectionDAG] Make use of KnownBits::commonBits. NFC.
Differential Revision: https://reviews.llvm.org/D94587
2021-01-14 14:02:43 +00:00
Florian Hahn
4aa6e58a81 [InferFunctionAttrs] Improve CHECK variable names (NFC). 2021-01-14 13:53:51 +00:00
Alexandre Ganea
358e11b98e Revert "Fix llvm::Optional build breaks in MSVC using std::is_trivially_copyable"
This reverts commit 854f0984f0b7ab9a9a541a4bcda7ea173e4113d3.

This breaks compilation with clang-cl on Windows, while in a MSVC 16.8 cmd.exe.
This also breaks PPC: http://lab.llvm.org:8011/#/builders/93/builds/1435
And: https://reviews.llvm.org/D93510#2497737
2021-01-14 08:35:38 -05:00
Nigel Perks
ac5c73680f Change XCore code owner.
Discussion: https://lists.llvm.org/pipermail/llvm-dev/2021-January/147603.html
2021-01-14 12:13:48 +00:00
Simon Pilgrim
f6ea817269 [DAG] visitVECTOR_SHUFFLE - MergeInnerShuffle - reset shuffle ops and reorder early-out and second op matching. NFCI.
I'm hoping to reuse MergeInnerShuffle in some other folds - so ensure the candidate ops/mask are reset at the start of each run.

Also, move the second op matching before bailing to make it simpler to try to match other things afterward.
2021-01-14 11:55:20 +00:00
Simon Pilgrim
5a57f8ab91 [X86] Improve sum-of-reductions v4f32 test coverage
Ensure that the v4f32 reductions use a -0.0f start value and add fast-math test variant.
2021-01-14 11:05:19 +00:00
Simon Pilgrim
09ec0447e1 [DAG] visitVECTOR_SHUFFLE - pull out shuffle merging code into lambda helper. NFCI.
Make it easier to reuse in a future patch.
2021-01-14 11:05:19 +00:00
Bjorn Pettersson
5a1624141a [SLP] Don't vectorize stores of non-packed types (like i1, i2)
In the spirit of commit fc783e91e0c0696e (llvm-svn: 248943) we
shouldn't vectorize stores of non-packed types (i.e. types that
has padding between consecutive variables in a scalar layout,
but being packed in a vector layout).

The problem was detected as a miscompile in a downstream test case.

Reviewed By: anton-afanasyev

Differential Revision: https://reviews.llvm.org/D94446
2021-01-14 11:30:33 +01:00
Andy Wingo
a312ae5a63 [lld][WebAssembly] Add support for handling table symbols
This commit adds table symbol support in a partial way, while still
including some special cases for the __indirect_function_table symbol.
No change in tests.

Differential Revision: https://reviews.llvm.org/D94075
2021-01-14 11:13:13 +01:00
Florian Hahn
a94ec580f1 [LTO] Expose opt() in LTOBackend (NFC).
Exposing opt() which runs middle-end LTO optimzation allows re-using it
in LTOCodeGenerator.

Reviewed By: steven_wu

Differential Revision: https://reviews.llvm.org/D94486
2021-01-14 09:53:41 +00:00
Lucas Prates
a8aeccfb29 [AArch64] Adding ACLE intrinsics for the LS64 extension
This introduces the ARMv8.7-A LS64 extension's intrinsics for 64 bytes
atomic loads and stores: `__arm_ld64b`, `__arm_st64b`, `__arm_st64bv`,
and `__arm_st64bv0`. These are selected into the LS64 instructions
LD64B, ST64B, ST64BV and ST64BV0, respectively.

Based on patches written by Simon Tatham.

Reviewed By: tmatheson

Differential Revision: https://reviews.llvm.org/D93232
2021-01-14 09:43:58 +00:00
David Stuttard
484b6eecca [NFC][AsmPrinter] Windows warning: Use explicit cast
static_cast for uint64_t to unsigned gives a MS VC build warning
for Windows:

warning C4309: 'static_cast': truncation of constant value

Use an explicit cast instead.

Change-Id: I692d335b4913070686a102780c1fb05b893a2f69

Differential Revision: https://reviews.llvm.org/D94592
2021-01-14 09:10:31 +00:00
Daniel Paoliello
1d9b216262 Fix unused variable in CoroFrame.cpp when building Release with GCC 10
When building with GCC 10, the following warning is reported:

```
/llvm-project/llvm/lib/Transforms/Coroutines/CoroFrame.cpp:1527:28: warning: unused variable ‘CS’ [-Wunused-variable]
 1527 |       if (CatchSwitchInst *CS =
```

This change adds a cast to `void` to avoid the warning.

Reviewed By: lxfind

Differential Revision: https://reviews.llvm.org/D94456
2021-01-13 22:53:25 -08:00
Duncan P. N. Exon Smith
03b8526e35 ADT: Reduce code duplication in SmallVector by calling reserve and clear, NFC 2021-01-13 21:10:31 -08:00
Duncan P. N. Exon Smith
a94b40b819 ADT: Reduce code duplication in SmallVector by reusing reserve, NFC 2021-01-13 20:52:57 -08:00
Duncan P. N. Exon Smith
1f680ae2d9 ADT: Reduce code duplication in SmallVector::resize by using pop_back_n, NFC 2021-01-13 20:50:00 -08:00
Duncan P. N. Exon Smith
48a93fb6cc ADT: Fix reference invalidation in SmallVector::resize
For small enough, trivially copyable `T`, take the parameter by-value in
`SmallVector::resize`.  Otherwise, when growing, update the arugment
appropriately.

Differential Revision: https://reviews.llvm.org/D93781
2021-01-13 20:48:08 -08:00
Jordan Rupprecht
1518e520f8 [NFC] Fix -Wsometimes-uninitialized
After 49142991a685bd427d7e877c29c77371dfb7634c, clang detects that MUL may be uninitialized. Set it to nullptr to suppress this check.

Adding an assert to check that it is ultimately set fails two test cases. Since this is not a new issue, leave the assertion commented out until a code owner can fix the bug. The two failing test cases are noted in the assertion comment.
2021-01-13 20:32:38 -08:00
Duncan P. N. Exon Smith
f269bb04a5 ADT: Fix reference invalidation in N-element SmallVector::append and insert
For small enough, trivially copyable `T`, take the parameter by-value in
`SmallVector::append` and `SmallVector::insert`.  Otherwise, when
growing, update the arugment appropriately.

Differential Revision: https://reviews.llvm.org/D93780
2021-01-13 20:00:44 -08:00
Duncan P. N. Exon Smith
9e6be04b5b Reapply "ADT: Fix reference invalidation in SmallVector::push_back and single-element insert"
This reverts commit 56d1ffb927d03958a7a31442596df749264a7792, reapplying
9abac60309006db00eca0af406c2e16bef26807c, removing insert_one_maybe_copy
and using a helper called forward_value_param instead. This avoids use
of `std::is_same` (or any SFINAE), so I'm hoping it's more portable and
MSVC will be happier.

Original commit message follows:

For small enough, trivially copyable `T`, take the argument by value in
`SmallVector::push_back` and copy it when forwarding to
`SmallVector::insert_one_impl`. Otherwise, when growing, update the
argument appropriately.

Differential Revision: https://reviews.llvm.org/D93779
2021-01-13 19:45:39 -08:00
Kazu Hirata
d553ab9e63 [llvm] Use std::any_of (NFC) 2021-01-13 19:14:44 -08:00