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Commit Graph

74516 Commits

Author SHA1 Message Date
Craig Topper
19cca98c0c Make RecordKeeper::addClass/addDef take unique_ptrs instead of creating one internally.
llvm-svn: 222948
2014-11-29 05:52:51 +00:00
Craig Topper
2d10991762 Use unique_ptr to remove some explicit deletes on some error case returns. At least one spot of weird ownership passing that needs some future cleanup.
llvm-svn: 222947
2014-11-29 05:31:10 +00:00
Duncan P. N. Exon Smith
57cead164b DebugIR: Delete -debug-ir
llvm-svn: 222945
2014-11-29 03:15:47 +00:00
Matt Arsenault
5c2fb0e261 R600/SI: Fix assertion on sign extend of 3 vectors
This was trying to create an MVT with 3x vectors which
created an invalid EVT

llvm-svn: 222942
2014-11-28 22:51:38 +00:00
Duncan P. N. Exon Smith
73ce6dbb2b Revert "Masked Vector Load and Store Intrinsics."
This reverts commit r222632 (and follow-up r222636), which caused a host
of LNT failures on an internal bot.  I'll respond to the commit on the
list with a reproduction of one of the failures.

Conflicts:
	lib/Target/X86/X86TargetTransformInfo.cpp

llvm-svn: 222936
2014-11-28 21:29:14 +00:00
David Majnemer
87a17a0975 InstCombine: FoldOrOfICmps harder
We may be in a situation where the icmps might not be near each other in
a tree of or instructions.  Try to dig out related compare instructions
and see if they combine.

N.B.  This won't fire on deep trees of compares because rewritting the
tree might end up creating a net increase of IR.  We may have to resort
to something more sophisticated if this is a real problem.

llvm-svn: 222928
2014-11-28 19:58:29 +00:00
Bruno Cardoso Lopes
a072cee758 [LICM] Store sink and indirectbr instructions
Loop simplify skips exit-block insertion when exits contain indirectbr
instructions. This leads to an assertion in LICM when trying to sink
stores out of non-dedicated loop exits containing indirectbr
instructions. This patch fix this issue by re-checking for dedicated
exits in LICM prior to store sink attempts.

Differential Revision: http://reviews.llvm.org/D6414

rdar://problem/18943047

llvm-svn: 222927
2014-11-28 19:47:46 +00:00
Bruno Cardoso Lopes
02319ec9b1 [SwitchLowering] Handle multiple destinations on condensed case stmts
Switch cases statements with sequential values that branch to the same
destination BB may often be handled together in a single new source BB.
In this scenario we need to remove remaining incoming values from PHI
instructions in the destination BB, as to match the number of source
branches.

Differential Revision: http://reviews.llvm.org/D6415

rdar://problem/19040894

llvm-svn: 222926
2014-11-28 19:47:33 +00:00
Sanjay Patel
019be40c8c Enable FeatureFastUAMem for btver2
Allow unaligned 16-byte memop codegen for btver2. No functional changes for any other subtargets.

Replace the existing supposed small memcpy test with an actual test of a small memcpy. 
The previous test wasn't using FileCheck either.

This patch should allow us to close PR21541 ( http://llvm.org/bugs/show_bug.cgi?id=21541 ).

Differential Revision: http://reviews.llvm.org/D6360

llvm-svn: 222925
2014-11-28 18:40:18 +00:00
Rafael Espindola
880240ae91 Add back r222727 with a fix.
The original patch would fail when:

* A dst opaque type (%A) is matched with a src type (%A).
* A src opaque (%E) type is then speculatively matched with %A and the
  speculation fails afterward.
* When rolling back the speculation we would cancel the source %A to dest
  %A mapping.

The fix is to keep an explicit list of which resolutions are speculative.

Original message:

Fix overly aggressive type merging.

If we find out that two types are *not* isomorphic, we learn nothing about
opaque sub types in both the source and destination.

llvm-svn: 222923
2014-11-28 16:41:24 +00:00
Rafael Espindola
6128226dc5 Add an assert and use a range loop. NFC.
llvm-svn: 222922
2014-11-28 16:26:14 +00:00
Charlie Turner
dc3f8f7176 Fix wrong encoding of MRSBanked.
Patch by Matthew Wahab.

Change-Id: Ia2a001ca2760028ea360fe77b56f203a219eefbc
llvm-svn: 222920
2014-11-28 15:01:06 +00:00
Evgeniy Stepanov
118b7804cb [msan] Fix origin propagation for select of floats.
MSan does not assign origin for instrumentation temps (i.e. the ones that do
not come from the application code), but "select" instrumentation erroneously
tried to use one of those.

https://code.google.com/p/memory-sanitizer/issues/detail?id=78

llvm-svn: 222918
2014-11-28 11:17:58 +00:00
Ankur Garg
0bf088f50d Removed extra line from a comment to test first commit. NFC.
llvm-svn: 222916
2014-11-28 10:38:18 +00:00
Craig Topper
c8e385cf52 Add missing 'override' keyword.
llvm-svn: 222911
2014-11-28 03:58:26 +00:00
Tim Northover
98dae1ec10 Stop using ArrayRef of a const type.
I *think* this is what the GCC bots are complaining about.

llvm-svn: 222905
2014-11-27 21:29:20 +00:00
Tim Northover
e8b34aaff0 AArch64: treat [N x Ty] as a block during procedure calls.
The AAPCS treats small structs and homogeneous floating (or vector) aggregates
specially, and guarantees they either get passed as a contiguous block of
registers, or prevent any future use of those registers and get passed on the
stack.

This concept can fit quite neatly into LLVM's own type system, mapping an HFA
to [N x float] and so on, and small structs to [N x i64]. Doing so allows
front-ends to emit AAPCS compliant code without having to duplicate the
register counting logic.

llvm-svn: 222903
2014-11-27 21:02:42 +00:00
Zoran Jovanovic
15712f82b0 [mips][microMIPS] Implement SWM16 and LWM16 instructions
Differential Revision: http://reviews.llvm.org/D5579

llvm-svn: 222901
2014-11-27 18:28:59 +00:00
Jozef Kolek
c85a4a5656 [mips][microMIPS] Implement BREAK16 and SDBBP16 instructions
Patch by Radovan Obradovic.

Differential Revision: http://reviews.llvm.org/D5048

llvm-svn: 222900
2014-11-27 18:18:42 +00:00
Daniel Sanders
d7d5d4cdb1 [mips] Add synci instruction.
Patch by Amaury Pouly

Reviewers: dsanders

Reviewed By: dsanders

Subscribers: llvm-commits

Differential Revision: http://reviews.llvm.org/D6421

llvm-svn: 222899
2014-11-27 17:28:10 +00:00
Rafael Espindola
fe0669d419 Commit back the correct bits of r222760 (was r222538).
I also added a test.

Original message:

Allow FDE references outside the +/-2GB range supported by PC relative
offsets for code models other than small/medium. For JIT application,
memory layout is less controlled and can result in truncations
otherwise.

Patch from Akos Kiss.

Differential Revision: http://reviews.llvm.org/D6079

llvm-svn: 222897
2014-11-27 17:13:56 +00:00
Rafael Espindola
008818ce29 Revert "Reapply 222538 and update tests to explicitly request small code model and PIC:"
This reverts commit r222760.

It changed our behaviour on PIC so we don't match gas anymore. It also
included lots of unnecessary changes to tests.

If those changes are desirable, there should be an independent discussion
as they are out of scope for that patch.

I will recommit the other bits.

llvm-svn: 222896
2014-11-27 17:13:51 +00:00
Duncan P. N. Exon Smith
bcb91dbf3f Revert "Fix overly aggressive type merging."
This reverts commit r222727, which causes LTO bootstrap failures.

Last passing @ r222698:
http://lab.llvm.org:8080/green/job/clang-Rlto_master_build/532/

First failing @ r222843:
http://lab.llvm.org:8080/green/job/clang-Rlto_master_build/533/

Internal bootstraps pointed at a much narrower range: r222725 is
passing, and r222731 is failing.

LTO crashes while handling libclang.dylib:
http://lab.llvm.org:8080/green/job/clang-Rlto_master_build/533/consoleFull#-158682280549ba4694-19c4-4d7e-bec5-911270d8a58c

    GEP is not of right type for indices!
      %InfoObj.i.i = getelementptr inbounds %"class.llvm::OnDiskIterableChainedHashTable"* %.lcssa, i64 0, i32 0, i32 4, !dbg !123627
     %"class.clang::serialization::reader::ASTIdentifierLookupTrait" = type { %"class.clang::ASTReader.31859"*, %"class.clang::serialization::ModuleFile.31870"*, %"class.clang::IdentifierInfo"* }LLVM ERROR: Broken function found, compilation aborted!
    clang: error: linker command failed with exit code 1 (use -v to see invocation)

Looks like the new algorithm doesn't merge types aggressively enough.

llvm-svn: 222895
2014-11-27 17:01:10 +00:00
Erik Eckstein
b81721adb5 reinstate r222872: Peephole optimization in switch table lookup: reuse the guarding table comparison if possible.
Fixed missing dominance check.
Original commit message:

This optimization tries to reuse the generated compare instruction, if there is a comparison against the default value after the switch.
Example:
   if (idx < tablesize)
      r = table[idx]; // table does not contain default_value
   else
      r = default_value;
   if (r != default_value)
      ...
Is optimized to:
   cond = idx < tablesize;
   if (cond)
      r = table[idx];
   else
      r = default_value;
   if (cond)
      ...
Jump threading will then eliminate the second if(cond).

llvm-svn: 222891
2014-11-27 15:13:14 +00:00
Evgeniy Stepanov
a93bac024f [msan] Remove indirect call wrapping code.
This functionality was only used in MSanDR, which is deprecated.

llvm-svn: 222889
2014-11-27 14:54:02 +00:00
Jozef Kolek
90243462d4 [mips][microMIPS] Implement disassembler support for 16-bit instructions LI16, ADDIUR1SP, ADDIUR2 and ADDIUS5
Differential Revision: http://reviews.llvm.org/D6419

llvm-svn: 222887
2014-11-27 14:41:44 +00:00
Charlie Turner
e4a6c7fd89 Stop uppercasing build attribute data.
The string data for string-valued build attributes were being unconditionally
uppercased. There is no mention in the ARM ABI addenda about case conventions,
so it's technically implementation defined as to whether the data are
capitialised in some way or not. However, there are good reasons not to
captialise the data.

  * It's less work.
  * Some vendors may legitimately have case-sensitive checks for these
    attributes which would fail on LLVM generated object files.
  * There could be locale issues with uppercasing.

The original reasons for uppercasing appear to have stemmed from an
old codesourcery toolchain behaviour, see

http://comments.gmane.org/gmane.comp.compilers.llvm.cvs/87133

This patch makes the object file emitted no longer captialise string
data, it encodes as seen in the assembly source.

Change-Id: Ibe20dd6e60d2773d57ff72a78470839033aa5538
llvm-svn: 222882
2014-11-27 12:13:56 +00:00
Erik Eckstein
6a5635f3ac Revert "Peephole optimization in switch table lookup: reuse the guarding table comparison if possible."
It is breaking the clang bootstrag.

llvm-svn: 222877
2014-11-27 10:59:08 +00:00
Erik Eckstein
15d20044f2 Peephole optimization in switch table lookup: reuse the guarding table comparison if possible.
This optimization tries to reuse the generated compare instruction, if there is a comparison against the default value after the switch.
Example:
    if (idx < tablesize)
       r = table[idx]; // table does not contain default_value
    else
       r = default_value;
    if (r != default_value)
       ...
Is optimized to:
    cond = idx < tablesize;
    if (cond)
       r = table[idx];
    else
       r = default_value;
    if (cond)
       ...
\endcode
Jump threading will then eliminate the second if(cond).

llvm-svn: 222872
2014-11-27 08:33:51 +00:00
David Majnemer
9698d3487d InstCombine: Restore optimizations lost in r210006
This restores our ability to optimize:
(X & C) == 0 ? X ^ C : X  into  X | C
(X & C) != 0 ? X ^ C : X  into  X & ~C

llvm-svn: 222871
2014-11-27 07:25:21 +00:00
NAKAMURA Takumi
86d230cb48 Add LLVMObject to LLVMExecutionEngine.
llvm-svn: 222869
2014-11-27 06:36:22 +00:00
David Majnemer
d9ae958b9b InstSimplify: Restore optimizations lost in r210006
This restores our ability to optimize:
(X & C) ? X & ~C : X  into  X & ~C
(X & C) ? X : X & ~C  into  X
(X & C) ? X | C : X  into  X
(X & C) ? X : X | C  into  X | C

llvm-svn: 222868
2014-11-27 06:32:46 +00:00
Lang Hames
3f06ba3b2f [MCJIT] Remove the local symbol table from RuntimeDlyd - it's not needed.
All symbols have to be stored in the global symbol to enable
cross-rtdyld-instance linking, so the local symbol table content is
redundant.

llvm-svn: 222867
2014-11-27 05:40:13 +00:00
Lang Hames
63b80f5e8f [MCJIT] Replace JITEventListener::anchor (temporarily removed in r222861), and
move GDBRegistrationListener into ExecutionEngine to avoid layering violation.

llvm-svn: 222864
2014-11-27 01:41:16 +00:00
Lang Hames
8af711e954 [MCJIT] Remove JITEventListener's anchor until I can determine the right place
to put it. This should unbreak the Mips bots.

llvm-svn: 222861
2014-11-27 00:15:28 +00:00
Lang Hames
7d4e7a1733 [MCJIT] Move get-any-symbol-load-address logic out of RuntimeDyld and into
RuntimeDyldChecker.

RuntimeDyld instances should only provide lookup for locally defined
symbols.

llvm-svn: 222859
2014-11-27 00:12:28 +00:00
David Majnemer
7e9b94486e Revert "Added inst combine transforms for single bit tests from Chris's note"
This reverts commit r210006, it miscompiled libapr which is used in who
knows how many projects.

A test has been added to ensure that we don't regress again.

I'll work on a rewrite of what the optimization was trying to do later.

llvm-svn: 222856
2014-11-26 23:00:38 +00:00
Rui Ueyama
ab9d8be85c Object/COFF: Fix off-by-one error for object having lots of relocations
llvm-objdump printed out an error message for this off-by-one error,
but because it always exits with 0 whether or not it found an error,
the test (llvm-objdump/coff-many-relocs.test) succeeded.
I made llvm-objdump exit with EXIT_FAILURE when an error is found.

llvm-svn: 222852
2014-11-26 22:17:25 +00:00
Matt Arsenault
796e0c24e7 R600/SI: Use ZeroOrNegativeOneBooleanContent
This sort of doesn't matter since the setcc type is i1, but
this previously was using the default UndefinedBooleanContent. This
makes it more consistent with R600. This enables more optimizations
which typically give up on UndefinedBooleanContent. For example,
there is already a special case target DAG combine for
setcc + sext which can be eliminated in favor of what the generic
DAG combiner can do if it assumes boolean values are sign extended.
Since -1 is an inline immediate, using it is basically free and the
backend already uses it when a boolean value is needed in a wider type.

llvm-svn: 222850
2014-11-26 21:23:15 +00:00
Colin LeMahieu
0872710917 [Hexagon] Adding cmp* immediate form instructions.
llvm-svn: 222849
2014-11-26 19:43:12 +00:00
Jozef Kolek
ecfa20e7f7 [mips][microMIPS] Implement disassembler support for 16-bit instructions LBU16, LHU16, LW16, SB16, SH16 and SW16
Differential Revision: http://reviews.llvm.org/D6405

llvm-svn: 222847
2014-11-26 18:56:38 +00:00
Colin LeMahieu
1f8cdbb85d [Hexagon] Adding and64, or64, and xor64 instructions.
llvm-svn: 222846
2014-11-26 18:55:59 +00:00
Matt Arsenault
b4b33cf9de R600/SI: Create e64 versions of and/or/xor in SILowerI1Copies
This fixes moving boolean constants into registers before operating
on them. They get permuted and shrunk down to e32 anyway later. This
is a temporary fix until the patch that removes these pseudos is
committed.

llvm-svn: 222844
2014-11-26 18:18:28 +00:00
Lang Hames
b0f5c0e15c [MCJIT] Fix missing return statement.
llvm-svn: 222841
2014-11-26 17:21:41 +00:00
Lang Hames
787f3dbf64 [MCJIT] Reapply r222828 and r222810-r222812 with fix for MSVC move-op issues.
llvm-svn: 222840
2014-11-26 16:54:40 +00:00
Aaron Ballman
18c93c9af6 Reverting r222828 and r222810-r222812 as they broke the build on Windows.
http://bb.pgr.jp/builders/ninja-clang-i686-msc17-R/builds/11753

llvm-svn: 222833
2014-11-26 15:27:39 +00:00
Aaron Ballman
011e7b3c54 Removing a spurious semicolon; NFC
llvm-svn: 222830
2014-11-26 13:55:55 +00:00
Evgeniy Stepanov
f853256b9e Add missing "override".
Fixes compilation failure in r222810.

llvm-svn: 222828
2014-11-26 12:26:03 +00:00
Will Newton
da953f13b9 Update AArch64 ELF relocations to ABI 1.0
This mostly entails adding relocations, however there are a couple of
changes to existing relocations:

1. R_AARCH64_NONE is defined to be zero rather than 256

R_AARCH64_NONE has been defined to be zero for a long time elsewhere
e.g. binutils and glibc since the submission of the AArch64 port in
2012 so this is required for compatibility.

2. R_AARCH64_TLSDESC_ADR_PAGE renamed to R_AARCH64_TLSDESC_ADR_PAGE21

I don't think there is any way for relocation names to leak out of LLVM
so this should not break anything.

Tested with check-all with no regressions.

llvm-svn: 222821
2014-11-26 10:49:18 +00:00
Elena Demikhovsky
868b76ae69 AVX-512: Scalar ERI intrinsics
including SAE mode and memory operand.
Added AVX512_maskable_scalar template, that should cover all scalar instructions in the future.

The main difference between AVX512_maskable_scalar<> and AVX512_maskable<> is using X86select instead of vselect.
I need it, because I can't create vselect node for MVT::i1 mask for scalar instruction.

http://reviews.llvm.org/D6378

llvm-svn: 222820
2014-11-26 10:46:49 +00:00